標題: 雙軌的自時管線微處理器實作
A Self-timed Dual-rail Pipelined Microprocessor Implementation
作者: 蔡宏岳
陳昌居
資訊科學與工程研究所
關鍵字: 非同步電路;管線處理器;asynchronous;delay insensitive;dual rail;PIC
公開日期: 2006
摘要: 一非同步PIC18於2006年發表於國立交通大學。這顆命名為「APIC18」的微處理器乃基於延遲遲鈍 (delay-insensitive)模型開發設計,可廣泛應用於各種不穩定的環境,諸如工作電壓、溫度或是製程參數等。但受限於延遲遲鈍模型先天上的限制,此電路在設計上缺乏彈性、易受制肘,亦間接成為效能提升之瓶頸。 此篇論文闡述一全新的管線架構以改善前述之問題,藉由特殊的暫停機制,僅需少量額外電路即可在效能上獲得相當程度的提升。唯一令人扼腕的,在理論上它並非理想的延遲遲鈍,尚須滿足額外的時間假設。然而,就現階段的製程技術而論,要滿足此假設並非難事,故其電路之正確性亦是無庸置疑的。
In 2006, the asynchronous PIC18[1], APIC18, had been proposed in NCTU. It is a delay-insensitive (DI) implementation, and very robust to the environment, including supply voltage, temperature and processing parameter. However, because of the DI nature, it is inflexible that makes the circuits design difficult. In order to meet the DI constraints, it also limits the performance improvement. In this thesis, a new pipeline architecture is developed to improve the performance for original APIC18. A stall policy is proposed and added to our previous implementation. The asynchronous PIC18 with stall policy, the APIC18S, has higher performance than APIC18 with just a little overhead. However it slightly violates the DI model, but in practice it still operates correctly with present processing technology.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009317521
http://hdl.handle.net/11536/78732
Appears in Collections:Thesis


Files in This Item:

  1. 752101.pdf