標題: 超寬頻射頻關鍵積體電路之設計與分析
Design and Analysis of Key Radio Frequency Integrated Circuits for Ultra-Wideband Communication Systems
作者: 饒佩宗
Rao, Pei-Zong
鍾世忠
Chung, Shyh-Jong
電信工程研究所
關鍵字: 超寬頻;混頻器;頻率合成器;震盪器;除頻器;UWB;mixer;synthesizer;VCO;frequency divider
公開日期: 2009
摘要: 本篇論文提出了數種適用於超寬頻通訊系統的0.18 微米互補式金氧半製程關鍵積體電路元件的架構、分析與設計。其中包含了 (1)兩個高線性度之寬頻降頻器的分析與設計;(2)應用於超寬頻系統的全頻帶頻率合成器的設計;(3)具溫度補償效應的主動式電感電壓控制震盪器;(4)利用電流再利用技術的半動態除三電路。 首先談到的是第一種寬頻高線性度降頻器。此混頻器使用摺疊疊接式的吉伯特混頻器架構,此摺疊疊接式混頻器包含高線性度的轉導級搭配寬頻切換級,除了可以增加輸出訊號的擺幅之外,亦針對此混頻器的線性度做了理論及實務上的設計與分析。利用諧波平衡理論分析推導電路的轉導結構,推導出抑制三階諧波的條件進而達成線性度的提升。量測結果顯示,此寬頻降頻器於使用頻段範圍內的轉換增益為 3.3 ± 1.5 dB,等效輸入端之增益 1-dB 壓縮點(IP1dB)為-2.8 dBm,等效輸入端之三階互調失真點(IIP3)為 6.9 dBm。此寬頻降頻器的工作電壓為1.8伏特,共消耗功率14.4 mW。 此降頻器的晶片面積為 0.7 * 0.58 平方毫米。基於第一種提出的降頻器的成果,第二種寬頻的降頻器再搭配上整合於晶片內的寬頻主動式巴倫電路。在此提出的寬頻主動式巴倫電路的目的為於單端輸入訊號的情況之下,可以用來產生寬頻的雙端平衡輸出。利用寬頻主動式巴倫的小訊號模型推導出了精確的相位差關係式,進而推知此主動式巴倫於2 GHz到13 GHz的使用頻段範圍內可達到只有2 dB的增益差異及4度的相位差異。由量測結果顯示,此具有寬頻巴倫的寬頻降頻器的轉換增益為 6.9 ± 1.5 dB,等效輸入端之增益 1-dB 壓縮點(IP1dB)為-3.5 dBm,等效輸入端之三階互調失真點(IIP3)為 6.5 dBm,此寬頻降頻器的工作電壓為1.8伏特時,總共消耗25.7 mW。此降頻器的晶片面積為 0.85 * 0.57 平方毫米。 其次,本論文提出了一個應用於IEEE 802.15.3a協定之超寬頻頻率合成器。此應用多頻帶正交頻率多工技術的超寬頻頻率合成器主要由兩組鎖相迴路,一個半動態除七電路,以及一個鏡像抑制混波器所構成。模擬結果顯示此頻率合成器全頻帶的頻率切換時間均小於2 ns,諧波抑制能力為25 dBc以上,工作電壓1.3伏特時共消耗111 mW。此頻率合成器的晶片面積為 2.29 * 2.51 平方毫米。 再其次,本論文提出一個應用具溫度補償效應的主動式電感之電壓控制震盪器。利用具溫度補償效應的主動式電感,可降低環境溫度對主動式電感所造成因電流改變而影響感值的效應。量測結果顯示,此震盪器在外界溫度由-20oC到60oC的條件之下,震盪頻率的變異度只有0.99%。當中心頻率操作於2.4GHz時,離載波頻率1MHz的相位雜訊為-91 dBc/Hz。當中心頻率為2.25GHz 時,頻率操作範圍可達48.89%。此震盪器的晶片面積為0.19 * 0.195平方毫米。 最後,本論文提出了一個可應用於60-GHz超寬頻系統的半動態除三電路。此除頻器主要由一組吉伯特混頻器,一級靜態除頻器,以及輸入端的主動式巴倫所組成。其中混頻器的切換級亦同時為除頻器的電流源,進而達成電流再利用的共同結構。由實驗的結果分析得知,在1.5伏特的工作電壓操作時,功率消耗為12 mW。當輸入訊號功率為0 dBm 時,除頻範圍為1080MHz。
In this dissertation, the design methodologies and implementations of key radio frequency integrated circuits (RFICs) for ultra-wideband (UWB) communication systems are proposed. There are four parts in this thesis, including: (1) the analysis and design of two wideband high-linearity down conversion mixers, (2) the design of full-band synthesizer for UWB applications, (3) the design of active inductor based proportional to absolute temperature (PTAT) voltage-controlled oscillator (VCO), and (4) the design of current-reused divide-by-3 semi-dynamic frequency divider (SDFD). Firstly, a 2.4 to 10.7 GHz high-linearity CMOS down conversion mixer using 0.18-µm CMOS technology is demonstrated. The mixer employs a folded cascode Gilbert cell topology. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP3 and IP1dB, and exhibits more compact size than most of published works. This wideband mixer has the conversion gain of 3.3 ± 1.5 dB, input 1-dB compression point (IP1dB) of -2.8 dBm, and third-order input intercept point (IIP3) of 6.9 dBm under the power consumption of 14.4 mW from a 1.8 V power supply. The chip area is 0.7 * 0.58 mm2. The second wideband high-linearity mixer is operated from 2 to 11 GHz with wideband active baluns using 0.18-µm CMOS technology. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband high-linearity mixer has the conversion gain of 6.9 ± 1.5 dB, IP1dB of -3.5 dBm, and IIP3 of 6.5 dBm under the power consumption of 25.7 mW from a 1.8 V power supply. The chip area is 0.85 * 0.57 mm2. Secondly, an UWB CMOS frequency synthesizer architecture is proposed and to be realized by TSMC 0.18-µm process technology. It can produce 14 bands for multi-band orthogonal frequency division multiplexing (MB-OFDM) system with characteristics of low power consumption and short switching time. The proposed architecture is composed of two PLLs, one divide-by-7 divider, and one SSB quadrature mixer. The simulation result shows that the synthesizer produces the full 14 bands with output frequencies ranging from 3.432 GHz to 10.296 GHz, and is with less than 2 ns hopping time, less than -25 dBc spurious, and 111 mW power consumption from a 1.3 V power supply. The total area including pads is 2.29 * 2.51 mm2. Thirdly, an LC-tank voltage-controlled oscillator (VCO) with temperature compensation active inductors using 0.18-µm 1P6M CMOS technology is demonstrated. A cascode-grounded active inductor circuit topology with the PTAT current sources was adopted, which is used to improve the temperature effect on the inductance of the active inductor. The measured variation of the oscillating frequency is within 0.99 % while the temperature varies from -20 to +60oC. The measured phase noise is -91 dBc/Hz at 1MHz offset when the oscillating frequency is at 2.4 GHz. The proposed circuit provides an oscillating frequency from 1.7 GHz to 2.8 GHz, exhibiting a 48% tunable frequency ranges. The active LC-tank VCO occupies a small active area of 190 * 195 µm2 due to the absence of passive inductors. Finally, a divide-by-3 SDFD with active balun is presented using the current-reused technique. The proposed SDFD is composed of a Gilbert cell mixer, one stage of static divider, and an active balun. The local oscillator (LO) switching stage of Gilbert cell mixer is also the current sources of the static frequency divider to construct the current-reused architecture. At the incident power of 0 dBm, this frequency divider operates the maximum bandwidth of 1080 MHz from 21.48 to 22.56 GHz. The power consumption of the divider core fabricated in TSMC 0.18-µm CMOS process is 12 mW from 1.5 V supply.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009313816
http://hdl.handle.net/11536/78472
Appears in Collections:Thesis


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