標題: 0.18μm互補式金氧半導體高頻壓控振盪器與鎖相迴路設計
0.18μm CMOS High Frequency Voltage-Controlled Oscillator and Phase-Locked Loop Design
作者: 許敦智
Tun-Chih Hsu
鍾世忠
Shyh-Jong Chung
電信工程研究所
關鍵字: 壓控振盪器;鎖相迴路;Voltage-Controlled Oscillator;Phase-Locked Loop
公開日期: 2005
摘要: 本論文分為壓控振盪器與鎖相迴路兩個部份。利用TSMC 0.18μm RF CMOS製程完成可應用於UWB系統之高頻壓控振盪器與鎖相迴路電路設計。 第一部份設計兩種不同電路特性的正交輸出壓控振盪器;第一種振盪器採用的電路架構為互補式交錯耦合對,量測結果頻率可調範圍為6.1GHz~6.5GHz,相位雜訊@1MHz offset為 -110dBc/Hz,功率消耗14.4mW,輸出功率約-17dBm。第二種振盪器採用的設計方法為電流再利用方式降低一般正交輸出壓控振盪器耗功率的缺點,量測結果頻率可調範圍為6.4GHz~6.7GHz,功率消耗為6.8mW,相位雜訊@1MHz offset為-106dBc/Hz,輸出功率約-11dBm。 第二部份設計兩種可應用於UWB系統之鎖相迴路。鎖相迴路輸出頻率為7.92GHz與3.96GHz且有一組互為正交的I/Q訊號:第一種電路第一級採用的除頻器為主樸式偶合閘(CML divider)電路,優點在於有良好的正交輸出信號特性,不過缺點是功率消耗大,整個迴路模擬結果功率消耗為13.5mW,其中第一級除頻器就佔了9.9mW。第二種鎖相迴路採用的第一級除頻器為真單相時脈(TSPC divider),其優點在於低功率消耗,不過輸出信號的正交特性跟輸入信號有關,整個迴路模擬結果功率消耗為6.8mW。
The thesis consists of two part: voltage-controlled oscillator(VCO) and phase-locked loop(PLL). Utilize TSMC 0.18μm RF CMOS Technology to be made high-frequency voltage-controlled oscillator and phase-locked loop which can be applied to UWB system. The first part designs two kinds of quadrature VCOs(QVCOs) which have different circuit characteristics. The first kind of QVCO adopts complementary cross-coupled pair. The measured tunning range is 6.1GHz~6.5GHz, phase noise is -110dBc/Hz at 1MHz offset , power consumption is 14.4mW, and output power is -17dBm under 1.8V supply. The second kind of QVCO adopts current-reuse topology. The measured tuning range is 6.4GHz~6.7GHz, phase noise is -106 dBc/Hz at 1MHz offset, power consumption is 6.8mW, and output power is -11dBm under 1.4V supply. The second part designs two kinds of PLLs that can be applied to UWB system. PLLs output frequency is 7.92GHz and 3.96GHz, including I/Q signals. The first kind of PLL adopts current mode logic(CML) divider at the 1st stage divider. Its avantage is perfect I/Q signal output but power consumption is large. The whole loop simulated power dissipation is 13.5mW, which CML divider is 9.9mW. The second kind of PLL uses a true single phase clock(TSPC) divider at 1st stage divider. Its advantage is low power consumption but output signal I/Q characteristic depends on its input signals. The whole loop simulated power dissipation is 6.8mW.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009313577
http://hdl.handle.net/11536/78392
顯示於類別:畢業論文


文件中的檔案:

  1. 357701.pdf