Title: 每秒一百億次取樣四位元類比數位與數位類比轉換器之設計
Design of 10 GS/s 4-bits ADC and DAC
Authors: 黃鼎鈞
Ding-Jyun Huang
Hao-Chiao Hong
Keywords: 快閃式類比數位轉換器;電流式數位類比轉換器;高速;傳輸鏈;Flash ADC;Current Steering DAC;CML
Issue Date: 2006
Abstract: 本論文提出利用 TSMC 0.13μm CMOS RF製程實現一4位元 10GS/s類比數位轉換器與一4位元 10GS/s數位類比轉換器,在數位電路上使用電流式邏輯電路來使整個數位電路操作在較低的擺幅,使電路可以高速下運作,並且有較低的電源抖動量同時有較低的功率消耗,也使用了管線的技巧來解決邏輯閘串接太多級導致延遲時間太長的問題,且在類比前置放大器上使用主動負迴授的技巧來使其達到高頻寬且較低的消耗功率,同時也在數位電路與類比電路上都使用全差動式的架構來最小化共模雜訊與偶次諧波失真的影響,在電源1.2伏特且時脈10GHz的情形下模擬結果呈現類比數位轉換器在輸入1GHz時ENOB達到3.87位元,同樣的數位類比轉換器在輸入1GHz 其SNDR與SFDR分別達到25.6dB與36dBc,而類比數位轉換器與數位類比轉換器的各別消耗功率為225mW與152mW。
This paper presents a 4-bit 10GS/s flash analog-to-digital converter (ADC) and a current steering 4-bit 10GS/s digital-to-analog converter (DAC) are designed and simulated with 0.13µm CMOS RF technology. Digital circuitry achieves low-swing operation by using the current mode logic (CML), which results in higher speed, lower power-ground bounce, as well as less power. Waveform pipeline concept is used to solve the limited latency for the logic gates. Active-feedback technique makes the analog pre-amplifiers achieve higher bandwidth with lower power consumption. Both analog and digital circuits benefit from fully differential architecture which minimizes their common-mode noise and even harmonics. Simulation results show that under a 1.2V supply voltage and operating at 10GHz, the ADC achieves an ENOB of 3.87bits with a 1GHz sinusoidal input. Meanwhile, the DAC has an SNDR of 25.6dB and an SFDR of 36dBc with a similar 1GHz digital stimulus. The ADC and DAC only dissipate 210mW and 142mW respectively.
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