標題: 適用於Serial-ATA之展頻時脈產生器及其內建自我測試電路
A Spread Spectrum Clock Generator and Built-in-Self-Test Circuit for Serial-ATA
作者: 周楙軒
MaoHsuan Chou
蘇朝琴
ChauChin Su
電控工程研究所
關鍵字: 除小數頻率合成器;展頻時脈產生器;內建自我測試電路;鎖相迴路;三角積分調變器;fractional-N frequency synthesizer;spread spectrum clock generator;built-in-self-test;phase-locked loop;sigma-delta modulator
公開日期: 2006
摘要: 隨著對高速傳輸速率需求的不斷提升,高速時脈信號所造成的電磁干擾(Electro-Magnetic Interference, EMI)成為不可忽視的問題。在常見的外部儲存規格Serial AT Attachment (Serial-ATA)中,系統要求資料傳輸時的時脈頻率具有5000 ppm的展頻量與30~33 kHz之三角波調變率。展頻技術即是利用對時脈信號頻率做調變以有效降低電磁干擾。 在本論文中,我們提出一個符合Serial-ATA規格並適用於6Gbps資料發送器之展頻時脈產生器(Spread Spectrum Clock Generator, SSCG)及其內建自我測試(Built-in-Self-Test, BIST)電路。我們使用一個具備三階三角積分調變器的除小數頻率合成器來實現展頻時脈產生器,使用數位式三角積分調變技術可將量化雜訊調變到高頻以減少spur現象。為了減少展頻時脈產生器的相位跳動,我們採用相位調變的方式來達到展頻的效果。展頻時脈產生器的內建自我測試電路是用數位的方式偵測展頻時脈產生器的頻率變動,藉由此測試電路可以簡單的測試出展頻時脈產生器是否正常操作。 我們使用TSMC CMOS 0.18 μm製程實現了一個1.2 GHz 10個phases,具有5000 ppm、30 kHz三角波調變的展頻時脈產生器及其內建自我測試電路。在非展頻情況所量測到的時脈抖動peak-to-peak jitter為48 ps;RMS jitter 為7.226 ps。在展頻模式下,頻譜上的時脈峰高能量降低了21.633 dB。
As operating at high frequencies, currents and voltages present in the circuits and the signal traces lead to a great Electro-Magnetic Interference (EMI). In Serial AT Attachment (Serial-ATA), one of the popular external storage specifications, it requires a wide spreading of 5000 ppm at a 30~33 kHz triangular modulation rate. The Spread Spectrum Clock Generator (SSCG) is a special technique of frequency modulation to reduce EMI effectively. In this thesis, we propose a SSCG for 6Gbps transceiver and its Built-in-Self-Test (BIST) circuit for Serial-ATA specification. We use a fractional-N frequency synthesizer with a digital third-order MASH 1-1-1 sigma-delta modulator to accomplish the spread spectrum function. The use of digital sigma-delta modulation technique in the fractional-N frequency synthesizer can eliminate spurs. Using phase modulation to spread the spectrum can reduce the phase jump of the SSCG. The BIST circuit for SSCG is a digital approach to detect the frequency variation of the SSCG, it can tests if the SSCG work or not effectively and precisely. The SSCG which has 1.2 GHz 10 phases, a 5000 ppm down spread and a 30 kHz triangular modulation rate. The BIST circuit are implemented using TSMC CMOS 0.18 μm technology. The measurement results show that the non spreading clock has a peak-to-peak jitter of 48 ps, a RMS jitter of 7.226 ps, and a peak amplitude reduction of 21.633 dB in the spread spectrum mode.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009312579
http://hdl.handle.net/11536/78266
Appears in Collections:Thesis


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