Mechanical Stress Assessment and Physical Model Development in Strained MOSFETs
|關鍵字:||機械應力;佈局;穿隧電流;摻雜擴散;氧化層缺陷;Mechanical Stress;Layout;Direct Tunneling Current;Dopant Diffusion;Oxide Trap|
Recently, mechanical stress in MOSFETs has gained much attention due to significant changes in electrical performance (mobility, drive capability, leakage etc.) and process issues (dopant diffusion, gate oxide integrity etc.). Therefore, this dissertation is aimed at demonstrating how to measure stress quantities in each part of the devices and address the induced changes. Based on the proposed methods, the underlying physical framework can be established while meeting the above issues. We first measure the conduction-band electron direct tunneling current through 1.27-nm gate oxide of n-MOSFETs that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to channel stress. To examine the accuracy of the method, a link with the mobility measurement on the same device is conducted. The resulting piezoresistance coefficient is shown to be in good agreement with literature values. The layout technique used is validated as well. Then, gate direct tunneling current under STI compressive stress is measured in a wide range of the drawn gate width W (= 0.11, 0.24, 0.6, 1.0 and 10 □m). The apparent gate current per unit width exhibits an increasing trend with decreasing W. In this narrowing direction, two fundamentally different effects are encountered: One of the delta width (□W) near the STI edge and one of the enhanced STI stress in the channel. To distinguish between the two effects, a new analytical width-dependent direct tunneling model is developed and applied. Reasonable agreement with data is achieved. The resulting delta width effect is found to dominate over the stress effect especially in the narrow devices, while for the wide ones, they will be comparable. The extracted □W and the underlying channel stress (with the uncertainties identified) straightforwardly produce a good fitting of the drain current variation counterpart. Specifically, it is justified that the delta width and STI stress are co-operative in constituting gate current variation but both have opposite effects on the drain current one. Third, drain subthreshold current is measured as a function of the gate edge to STI spacing and is transformed into the source/drain extension corner stress. The extracted local stress is quantitatively reasonable with those of the channel as created by the gate direct tunneling measurement in inversion, and the mobility measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate-to-source/drain-extension overlap length. Particularly, a retarded diffusion length and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is therefore reached, expressing the lateral diffusion length as a function of the corner stress. Finally, low-frequency noise measurement on p-channel MOSFETs yields the density of the gate-oxide interface states, exhibiting a decreasing trend with increasing STI tensile stress in the channel width direction. Two plausible physical origins of the interface-state density suppression in narrow devices are proposed: relaxed interface strain and reduced excess silicon per unit area during the thermal oxidation.
|Appears in Collections:||Thesis|
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