標題: 超寬頻無線網路應用之單一鎖相廻路頻率合成器設計
Single Phase-Locked Loop Frequency Synthesizer Design for Ultra-wideband Wireless Applications
作者: 賴俊憲
Jiun-Shian Lai
溫瓌岸
溫文燊
Kuei-Ann Wen
Wen-Shen Wuen
電子研究所
關鍵字: 頻率合成器;鎖相廻路;UWB;synthesizer;PLL;VCO
公開日期: 2005
摘要: 本論文完成一個可以合成UWB全部頻帶的頻率合成器設計.其中,為了防止因使用多組鎖相廻路而造成有多組電壓控制震盪器產生雜訊的互相干擾,本架構只使用了一組鎖相廻路.鎖相廻路中使用了連續的除二電路來產生合成UWB頻帶所需的中間頻率,這可減少混波器使用的數量並達到快速切換時間的要求.此外為了濾除不必要的突波雜訊,一組除二電路放置在混波器的下一級來減輕這個問題,且在輸出級有電感電容共振腔當作帶通濾波器來去除雜訊,其中電感電容共振腔還有負電阻和使用電感開關來提高操作的頻率範圍和更有效的去除雜訊.最後,突波雜訊在所有的頻帶都可被壓制在比-24dbc以下.
A CMOS frequency synthesizer which synthesizes all band groups of the ultra-wideband (UWB) system is presented. Only one phase-locked loop is used in this synthesizer to reduce interference of VCOs in multi-PLL frequency synthesizers. Divide-by-two circuit chains are used in the PLL to generate intermediate frequencies and reduce the numbers of required single-sideband (SSB) mixers for all-band frequency synthesis and thus achieve fast switching time. To suppress spurious emissions, the frequency synthesizer employs dividers and SSB mixers in the signal generation path. LC resonant loads at the output buffer together with negative resistances and switching inductors help to suppress more spurious signals and operate in wider frequency range. The spurious suppression is better than -24dBc in all band groups.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311690
http://hdl.handle.net/11536/78162
Appears in Collections:Thesis


Files in This Item:

  1. 169001.pdf