標題: 適用於H.264解碼器的可調式雙層外部記憶體管理器
A Flexible Two-Layer External Memory Management for H.264/AVC Decoder
作者: 張長軒
Chang-hsuan Chang
黃威
Wei Hwang
電子研究所
關鍵字: 記憶體管理器;memory controller;H.264/AVC decoder
公開日期: 2005
摘要: 在H.264解碼器中有大量的資料需要去存取記憶體,外部記憶體資料存取所需的時間和功率消耗對於整個H.264系統的效能影響很大,因為外部記憶體受到頻寬的限制所以外部記憶體的效能對於系統仍然是個瓶頸.在H.264解碼器中為了達到即時播放的效果,如何設計一個良好的記憶體子系統變的十分重要. 在這篇論文中,我門針對H.264解碼器提出了一個計憶體子系統,這個子系統包含了一個可調變的記憶體控制器,靜態隨機存取記憶體,雙倍數同步動態隨機存取記憶體,和一條匯流排. 子系統裡面的記憶體控制器除了要確保資料傳輸的正確性以外還要能改善外部記憶體的效能,我們所提出來的記憶體控制器共分成兩層,第一層是用來做位址轉換,這一層提供了一個存取記憶體的位址產生方法,這個方法可以就由減少記憶體中誤失的數目來達到節省功率的效果. 第二層是外部記憶體介面,除了產生適當的命令給記憶體外還可以降低因為記憶體誤失所耗費的時間,這個記憶體介面可以用來控制單倍數和雙倍數同步動態隨機存取記憶體,因為這個外部記憶體介面的可調變性,使用者可以快速的把這個介面隨著不同型態的外部記憶體整合到系統裡. 這個H.264解碼器中的記憶體控制器可以減少資料存取延遲時間到大約30%,而且頻寬的使用率可以從42%提升到51%左右.
In the H.264/AVC decoder there are large amount of data need to be fetched to/from the off-chip memory. The latency of accessing data and power consumption in the off-chip memory greatly affect the performance of the whole system. The performance of the off-chip memory is still the bottleneck of the video process due to the limited bandwidth. The real-time requirement in H.264/AVC decoder at level 4 result in the request of a well designed memory sub-system. In this thesis, we proposed a memory sub-system for the H.264/AVC decoder. This memory sub-system contains a flexible memory controller, SRAM, AHB-bus, and DDR SDRAM. This memory controller inside the memory sub-system not only keeps the correctness of the data transfer between the module and DRAM but is also responsible to improve the performance of the external memory. The proposed memory controller consists of two layers. The first layer is address translation which provide an efficient memory map method. This layer is designed to decrease the number of row-miss status and bank-miss status. By this way the power consumption can be saved. The second layer is external memory interface. Besides generate appropriate commands to the off-chip memory, this layer is used to increase bandwidth utilization and decrease the latency induced by the row-miss status and bank-miss status. This external memory interface is design to control the SDR SDRM and DDR SDRAM. Due to the flexibility of this EMI, the users can rapidly integrate this EMI into their system design with various kind of external memory. The experimental results of a H.264 decoder show that the proposed controller can further reduce access latency by approximately 30% and the memory utilization is accelerated from 42 % to 51%.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311679
http://hdl.handle.net/11536/78150
Appears in Collections:Thesis


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  1. 167902.pdf