標題: 積分式與充電式電容介面電路之評估Capacitive Interface Circuits Evaluated by Integrating and Charging Methods 作者: 蔡岳勳Yueh-hsun Tsai黃宇中Yu-Chung Huang電子研究所 關鍵字: 電容-電壓轉換器;電容-頻率轉換器;電容式感測器介面電路;capacitance-to-frequency converter;capacitance-to-voltage converter;capacitive sensor interface circuit 公開日期: 2007 摘要: 電容式感測器廣用於各種量測裝置。本論文中主要探討兩種不同的符合差動式電容感測器應用之介面電路，並從中選擇一個架構來完成晶片的實現。 積分式介面電路以交換電容式積分器為主要的架構。藉由差動式感測電容隨著環境影響產生的電容變化會使得積分器以不同的速度充放電，透過比較器產生工作週率的變化，便可反推得差動電容值。此轉換電路具有解析度高的優點。充電式介面電路以交換電容式取樣保持電路為主要的架構，在取樣階段分別以差動式感測電容取樣不同的參考電壓，在保持階段時，把取樣階段所儲存的電荷重新分配到感測電容中產生一個穩定的輸出電壓，此轉換電路的優點為速度快、實現容易且可大幅降低設計成本。 在本論文中，我們完成了兩種架構的設計與模擬，並在比較兩者的優缺點後，選擇了電荷重新分佈式的架構來進一步完成佈局以及離散時間模型的實現與量測。針對100pF的差動式電容，量側範圍為±100pF，輸出電壓範圍為1.47V至3.26V，誤差小於5%Capacitive sensors are widely adapted to various measuring equipments. The objective goal of this thesis is to design and analyze two different type of capacitive interface circuit and choose a structure to implement in discrete time model prototype chip. The architecture of integrating interface circuit is based on the switch-capacitor integrator. The charging and discharging speed varies with differential capacitance which senses the analog parameter. Through the comparator, the periodically charging and discharging behavior results in variation of duty cycle which achieve the readout of capacitance difference. The architecture can achieve high resolution. The architecture of charging interface circuit is based on switch-capacitor sample-and-hold circuit. During sample phase, the differential sensing capacitor sample two different reference voltage and redistribute them in hold phase and generate a stable output voltage. The architecture can achieve high speed, low cost, low power. In this thesis we complete the design and simulation of both architectures. From the discussion, a suitable architecture is chosen to be further implemented. The charging interface circuit is implemented with layout and discrete time model prototype chip. For 100pF nominate capacitance, the measuring range is ±100pF which correspond to voltage from 1.47V to 3.26V. The error of this capacitive interface circuit is less than 5%. URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311655http://hdl.handle.net/11536/78126 Appears in Collections: Thesis