標題: 奈米元件靜態隨機讀取記憶體特性之研究
Performance of SRAM with Nanoscale Transistors
作者: 呂建松
Chien-Sung Lu
黃調元
林鴻志
李義明
Tiao-Yuan Huang
Horng-Chih Lin
Yiming Li
電子研究所
關鍵字: 靜態隨機讀取記憶體;奈米元件;靜態雜訊邊際;敏感度;穩定度;混合模式元件模擬;SRAM;Nanoscale Transistors;Static Noise Margin;Sensitivity;Stability;Mixed-Mode Device Simulation
公開日期: 2005
摘要: 平面結構的金屬氧化物半導體場效電晶體目前是靜態記憶體的最常見的組成架構。不過,當設計規章向45奈米以下持續縮小時,傳統的平面的電晶體將遇到很多顯著的挑戰。立體(三維)架構的電晶體已經製造出來,並且證明有更好的電特性相較於傳統平面電晶體。對於靜態隨機讀取記憶體設計而言, 操作穩定度和記憶體所佔面積都是必須考慮的。靜態隨機讀取記憶體面積大約佔整個晶片區域的3 分之2,穩定度則是當製程和操作條件發生擾動時靜態隨機讀取記憶體特性的敏感性。為了增進靜態隨機讀取記憶體穩定度必須加大其面積,這兩者參數的關係是互相牽制的。 本文將探討使用三種不同結構的奈米級金屬氧化物半導體場效電晶體架構下靜態隨機讀取記憶體操作性能,三種結構分別是平面金屬氧化物半導體場效電晶體、絕緣層上矽鰭鱗式場效電晶體和全閘鰭鱗式場效電晶體,包含記憶體操作的穩定度和特性的敏感性分析將被討論。靜態雜訊邊際(SNM)參數將在考慮到量子效應下使用三維混合模式(mixed-mode)元件模擬軟體下加以萃取。首先,我們探討不同結構金屬氧化物半導體場效電晶體的本質特性和端點特性。此外,靜態雜訊邊際對於不同供應電壓,電晶體尺寸比率(cell ratio)和操作溫度的變化將被分析和比較。 當元件縮小到100奈米以下時,由於電晶體濃度摻雜,晶面粗糙和通道長度變動等所引起電晶體特性的擾動將開始影響到電路的特性和功能。不同的元件架構下的靜態隨機讀取記憶體穩定度的敏感性分析將被藉由一個有系統的統計方法被發展加以分析。藉由實驗設計,混合模式(連接的元件和電路)模擬技術,以及二次反應曲面模型,我們將專注對由於通道長度變化所產生的靜態雜訊邊際擾動加以探討。 本研究提供一個方法探討不同元件結構所架構的靜態隨機讀取記憶體的特性。在尚未有元件完整模型存在情況下,我們可以使用三維混合模式元件模擬對新的元件結構所架構的靜態隨機讀取記憶體的穩定度加以研究。對於電路特性擾動的探討,可藉由實驗設計和反應曲面模型的建立達到。總之,本文提供一個系統化的統計方法去探討奈米級金屬氧化物半導體場效電晶體架構下靜態隨機讀取記憶體操作性能。在時間、成本、效率的考量上,此方法顯得很有經濟效益。
Silicon-based planar MOSFETs have been the building block for SRAM. However, as the design rule continuously shrank down beyond the 45 nm, conventional planar CMOS devices encounter significant challenges. Many three-dimensional (3D) structure transistors, such as the bulk fin field-effect transistor (Bulk FinFET), SOI fin field-effect transistor (SOI FinFET), multiple-gate FinFET, and surrounding-gate nanowire FinFET (Nanowire FinFET) have been proposed, fabricated, and demonstrated more attractive electrical characteristics than that of single-gate planar devices. Two aspects are important for SRAM cell design: the cell area and the stability of the cell. The cell area determines about two-third of the total chip area. The cell stability determines the soft-error rate and the sensitivity of the memory to process tolerance and operating conditions. The two aspects are interdependent since designing a cell for improved stability invariably requires a larger cell area. In this thesis, we study the performance of 6-T SRAM cell with three different building 32 nm devices, planar MOSFETs, SOI FinFETs, and nanowire FinFETs. The stability and sensitivity analysis will be discussed. Static noise margin (SNM) of SRAM is computational investigated and compared by using a mixed-model three-dimensional device simulation with considering quantum mechanical effects. We firstly analyze and compare the intrinsic and terminal characteristics for the three different transistors in SRAM cells. Also, the SNM of SRAM during both hold and read modes is explored for the device with respect to different supply voltage , cell ratio, and operation temperature. With the scaling of conventional CMOS devices to sub-100 nm and beyond, the variations of the transistor characteristics due to local and non-local effects, such as the random dopants, the critical dimension of channel length, the interface roughness, and line edge roughness (LER) start to adversely affect the yield and functionality of the corresponding circuits. In this thesis, a systematical method for sensitivity analysis of SRAM cells with different device structures is developed. Based on a design of experiment (DOE), a mixed-mode (i.e., coupled device and circuit) simulation, and a response surface model (RSM), performances of 6T SRAM cells are explored with respect to static noise margin (SNM). Taking the channel length of different transistors in a 6-T SRAM cell as significant variables, a SNM response surface model is constructed. With the developed SNM model, the impact of channel length variation on SNM is evaluated. Finally, the purpose of this study is to provide a systematically statistical method to analysis the performance of the SRAM cell using nano-scale device structures. The stability of SRAM cells is explored by a 3D mixed-mode simulation. The sensitivity analysis of SNM will be studied by the combination of design of experiment and second-order response surface model. We believe that he design of 6-T SRAM cell with nanowire FinFETs is a promising approach in sub-45 nm CMOS devices era.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311566
http://hdl.handle.net/11536/78038
Appears in Collections:Thesis