A Study of Hot-Carrier Reliability for Poly-Si Thin-Film Transistors Using a Novel Test Structure
|關鍵字:||熱載子效應;可靠度;測試結構;薄膜電晶體;hot carrier effect;reliability;test structure;poly-Si TFT|
A novel thin-film transistor test structure was fabricated and employed for monitoring the device hot-carrier (HC) degradations. Such test structure consists of three monitor transistors and one test transistor. The three monitor transistors have their source/drain pairs arranged in the direction perpendicular to the channel of the test transistor. This unique design allows us to monitor the degradation induced in different portions of the channel of the test transistor as it is undergone hot-carrier (HC) stress. Furthermore, it has been demonstrated that the unique design is capable of detecting the degradation characteristics of devices with very high sensitivity. In the experiments both static and AC HC stress tests were applied to the test transistor of the structures. Results of the static stress test show that the damage is mainly induced near the drain-side of the stressed channel, and most serious degradation of the test device occurs under static stress condition when VG/VD ratio is around 1/3. In the AC stress, the effects of several factors including frequency, rising time, falling time, and duty cycle, were investigated and discussed. In addition to the period while both gate and drain are being applied with high voltages, the transient stages are also found to play a major role in affecting the device characteristics. In the case when the pulsed voltage train is applied to the gate, extra degradation is induced in the voltage falling stage and becomes more significant as the falling time is decreased. When the pulsed voltage train is applied to the drain, voltage rising stages are the key factor for the degradation and the degradation increases with decreasing rising time. The generation of extra hot carriers during the transient stages is used to explain the findings.
|Appears in Collections:||Thesis|