標題: 利用一種新穎結構進行複晶矽薄膜電晶體之熱載子可靠性分析
A Study of Hot-Carrier Reliability for Poly-Si Thin-Film Transistors Using a Novel Test Structure
作者: 張凱翔
林鴻志
黃調元
電子研究所
關鍵字: 熱載子效應;可靠度;測試結構;薄膜電晶體;hot carrier effect;reliability;test structure;poly-Si TFT
公開日期: 2008
摘要: 一種新穎測試結構被提出用來觀察複晶矽薄膜電晶體經過熱載子測試後所造成元件性能的衰退狀況。此新穎的元件結構,主要是在傳統結構通道的垂直方向額外做了三組感測電晶體。當測試元件在經過熱載子施壓時,利用感測電晶體來偵測通道不同區域的受損情況。除證實測試結構具有直接解析不同區域的受損差異外,實驗中也發現,由於感測電晶體能有效偵測元件早期受損的情形,因此具有提高偵測靈敏度之能力。 在實驗中將對此測試結構施以直流和交流應力去分析通道上不同區域的衰退機制。在直流應力的結果顯示,當施以閘極直流偏壓為汲極的三分之ㄧ時,此時元件受損程度最為嚴重,且受損位置主要位於靠近通道的汲極區域。在交流應力中,其頻率、上升時間、下降時間以及工作週率(duty cycle)等因素對於元件造成之影響進行深入研究與探討。在一個交流應力的週期中,除了當閘極和汲極偏壓維持在高電壓會對元件造成影響外,訊號切換過程同樣也扮演很重要的角色。在交流偏壓施加在閘極的情況下,發現閘極電壓由高切換至低的階段會對元件造成額外的傷害,並且隨著下降時間的減少傷害會變的更加顯著。而在交流偏壓施加在汲極的情況下,汲極電壓由低切換至高的階段扮演關鍵的因素,尤其當上升時間愈短時則元件的傷害會隨之增加。在交流應力下訊號切換過程所產生額外的熱載子效應,可以用來解釋我們所觀察到元件衰退的現象。
A novel thin-film transistor test structure was fabricated and employed for monitoring the device hot-carrier (HC) degradations. Such test structure consists of three monitor transistors and one test transistor. The three monitor transistors have their source/drain pairs arranged in the direction perpendicular to the channel of the test transistor. This unique design allows us to monitor the degradation induced in different portions of the channel of the test transistor as it is undergone hot-carrier (HC) stress. Furthermore, it has been demonstrated that the unique design is capable of detecting the degradation characteristics of devices with very high sensitivity. In the experiments both static and AC HC stress tests were applied to the test transistor of the structures. Results of the static stress test show that the damage is mainly induced near the drain-side of the stressed channel, and most serious degradation of the test device occurs under static stress condition when VG/VD ratio is around 1/3. In the AC stress, the effects of several factors including frequency, rising time, falling time, and duty cycle, were investigated and discussed. In addition to the period while both gate and drain are being applied with high voltages, the transient stages are also found to play a major role in affecting the device characteristics. In the case when the pulsed voltage train is applied to the gate, extra degradation is induced in the voltage falling stage and becomes more significant as the falling time is decreased. When the pulsed voltage train is applied to the drain, voltage rising stages are the key factor for the degradation and the degradation increases with decreasing rising time. The generation of extra hot carriers during the transient stages is used to explain the findings.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311562
http://hdl.handle.net/11536/78033
Appears in Collections:Thesis


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  1. 156201.pdf
  2. 156202.pdf
  3. 156203.pdf