標題: 不同前處理對氮氧化鉿(鋯)閘極介電層於鍺基板之電物性研究
The Electrical and Physical Properties of Hf(Zr)-oxynitride Gate Dielectrics on Ge Substrates with Various Surface Pretreatments
作者: 林哲弘
Je-Hung Lin
張俊彥
Chun-Yen Chang
電子研究所
關鍵字: 高介電係數;鍺基板;表面前處理;閘極介電層;氮氧化鉿;氮氧化鋯;high-k;Ge substrate;surface pretreatment;gate dielectric;HfOxNy;ZrOxNy
公開日期: 2005
摘要: 對於四氟化碳和氨氣電漿前處理以及二矽乙烷的鈍化前處理方法,我們有系統地研究此三種表面前處理對於氮氧化鉿以及氮氧化鋯閘極介電層在鍺基板上之電物性。 我們發現高介電係數材料與鍺基板的接面和矽基板的接面有不同熱化學的特性;在矽基板與氮氧化鋯之間的接面層會因高溫處理而成長,並且有助於鋯金屬矽化物的形成。相反的,在鍺基板與氮氧化鋯之間的接面層會因高溫處理而揮發,並且抑制鋯金屬鍺化物的形成,此外,由於接面層揮發使介電層所產生的局部凹陷現象,亦會損害高介電係數材料/鍺基板元件結構的電性。 高介電係數材料/鍺基板結構會有很差的熱穩定性主要是由於低品質的鍺原生氧化層,因此沉積介電質後的熱退火處理以及沉積金屬電極後的熱退火處理就被用來檢驗白金/高介電係數材料/鍺基板電容結構之熱穩定性。我們發現沉積介電質後的熱退火處理並不會增加鍺基板的捕捉缺陷( bulk traps ),而沉積金屬電極後的熱退火處理卻會使其增加。此外,這兩種熱退火處理都能削減接面載子捕捉密度( Dit )與縮小等效氧化層厚度,但此二種熱處理過程卻同時增加了閘極漏電流。 四氟化碳電漿前處理會使白金/高介電係數材料/鍺基板電容結構中的遲滯寬度與閘極漏電流增大,這很可能是由於接面載子捕捉密度以及表面粗糙度的增加。另一方面,氨氣電漿前處理卻壓縮了遲滯寬度,這應該與較少的氧化鍺和接面載子捕捉密度有關,另外,此種氮化過程也能減少氧化鍺的成長以及它的揮發,因而改善白金/高介電係數材料/鍺基板電容結構的熱穩定性。 在攝氏五百五十度下熱脫附十分鐘以及接下來的二矽乙烷鈍化前處理已經成功地消除鍺的原生氧化層,因此大大縮小了遲滯的寬度,但是在高頻的電容-電壓曲線圖中,有經過二矽乙烷鈍化前處理的試片卻呈現出低頻的電容-電壓特性曲線。然而,這些表面前處理解決了遲滯現象並且改善了白金/高介電係數材料/鍺基板電容結構的熱穩定性,因此持續最佳化接面特性應能改善電性以及實現鍺基板結合高介電係數材料之元件。
We have systematically investigated the electrical and physical properties of HfOxNy and ZrOxNy gate dielectrics on Ge substrates with different surface pretreatments, including CF4 plasma pretreatment, NH3 plasma pretreatment and Si2H6 passivation. We found that the interfacial layer of high-k/Si and high-k/Ge have distinct thermochemical properties; high temperature processing aided the interfacial layer growth and the formation of Zr–silicate in ZrOx(Ny)/Si gate stack. On the contrary, severe interfacial layer volatilization and the inhibition of Zr–germinate were found in ZrOx(Ny)/Ge system, moreover, the generated localized pits in deposited high-k films owing to the desorption of the interfacial layer might degrade the electrical properties of fabricated high-k/Ge devices. The poor thermal stability of high-k/Ge gate stacks is due to inherent poor quality of Ge native oxide. Two thermal processes PDA and PMA are included to examine the thermal stability of Pt/high-k/Ge capacitors. We found that the PDA process did not multiply the pre-existing bulk traps in Ge substrate but the PMA process increased them. Furthermore, both annealing processes were found to annihilate the amount of Dit and shrink the CET, but these thermal processed increased the gate leakage current at the same time. The CF4 plasma pretreatment enlarged the hysteresis width and gate leakage current of Pt/high-k/Ge capacitors, which were possibly due to the increment of Dit and surface roughness. On the other hand, the NH3 plasma pretreatment compressed the hysteresis width, which was related with less GeOx and Dit, moreover, this nitridation process improved the thermal stability of Pt/high-k/Ge capacitors by diminishing the formation of GeOx and their volatilization. The Ge native oxide was successful eliminated by thermal desorption at 550□C for 10 min and following Si2H6 passivation, which greatly reduced the hysteresis width of Pt/high-k/Ge capacitors, but the high frequency C-V curves of the Si2H6 passivation samples presented a low-frequency-like characteristic. However, those surface pretreatments solved the hysteresis effect and improved the thermal stability of Pt/high-k/Ge capacitors, thus the continuous optimization of the interface properties are expected to improve the electrical characterization and achieve the Ge device in combination with a high-k dielectric.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311530
http://hdl.handle.net/11536/78002
Appears in Collections:Thesis


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