標題: 前瞻非揮發性奈米點記憶體元件之製作與特性研究
Fabrication and Electrical Characterization of Advanced Nanocrystals Nonvolatile Memories
作者: 陳緯仁
Wei-Ren Chen
張俊彥
Chun-Yen Chang
電子研究所
關鍵字: 奈米點;矽氧氮氧矽 型態;非揮發性記憶體;鍺;矽化鎳;錳矽氧化物;多層;雙層;Nanocrystal;SONOS type;Nonvolatile memory;Ge;NiSi;MnSiO;multi layer;double layer
公開日期: 2008
摘要: 目前非揮發性記憶體在元件尺寸持續的微縮下,其需求為高密度記憶單元、低功率損耗、快速讀寫操作以及良好的可靠度(Reliability)。然而傳統浮動閘極(Floating gate)記憶體在操作過程中,穿遂氧化層產生漏電路徑會造成所有儲存電荷流失回到矽基版,隨著尺寸微縮這種情況會更糟,所以在資料保存時間(Retention)和耐操度(Endurance)的考量下,微縮穿遂氧化層的厚度是非常困難的。具非揮發性奈米點記憶體及SONOS記憶體被提出並希望可取代傳統浮動閘極記憶體,由於彼此分離的儲存點作為儲存中心,所以上述兩者可以有效改善小尺寸記憶體元件多次讀寫操作下的資料儲存能力。 在本論文中,主要提出三種不同性質的奈米點(鍺、矽化鎳與錳矽氧化物奈米點)材料來克服傳統非揮發性記憶體在微縮過程中會遭遇到的困難,我們首先提出一種矽鍺氧薄膜的堆疊結構作為鍺奈米點的自我析出層(Self-assembled layer),並應用在奈米點非揮發性記憶體上。在室溫環境中,利用濺鍍(Sputtering)矽鍺(Si0.5Ge0.5)混合靶材的方式來形成電荷儲存層,同時加入氬氣及氧氣一起共鍍,此方式可以成功的將氧氣原子摻入至矽鍺中形成矽鍺氧三元結構的薄膜,另外,在我們的實驗中,我們也發現在氮氣熱退火之前先疊加上一層氧化矽作為阻擋鍺揮發的阻擋層,此為使用矽鍺氧薄膜作為電荷儲存層的一個關鍵步驟。之後我們再利用氧、矽與鍺之間不同氧化競爭的現象,經由快速熱退火製成來形成均勻且高密度(~1012cm-2)的鍺奈米點埋藏於氧化層中。此鍺奈米點製程相對於傳統鍺奈米點製作,可以有效地防止鍺被過度氧化並且降低電荷儲存效率。同樣地,我們運用類似的鍺奈米點形成機制,在濺鍍的過程中將氧氣置換成氮氣,利用同樣的方式製作鍺奈米點且奈米點可以在析出過程被包覆在氮化矽(SiNx)的結構中,其記憶窗口比先前的鍺奈米點埋藏在氧化矽結構還顯著,此乃因為鍺奈米點埋在氮化矽為主的電荷儲存層裡,會與奈米點周圍的介電層產生額外的電荷儲存中心,進而增加記憶體整體效能,另外,我們比較這兩種結構的鍺奈米點記憶體,由於氮化矽能使儲存電荷均勻分佈於儲存層以降低庫倫斥力效應,所以在本研究中不論在電荷儲存能力與可靠度上,埋藏在氮化矽的鍺奈米點記憶體都展現較好的記憶體特性。 近年來已經發展了許多方法來形成奈米點記憶體,一般而言,大多數的方法都需要長時間且高溫的熱退火製程,這個步驟會影響現階段半導體製程中的熱預算和產能。因此在本論文中,我們使用一個簡單、低溫的製程方法來形成鎳氧矽化物(Ni-O-Si)和鎳矽氮化物(Ni-Si-N)奈米點,並將其應用於非揮發性記憶體元件上。我們一樣在氬氣和氧氣(Ar/O2)的環境中濺鍍混合鈀材Ni0.3Si0.7形成氧化矽(SiOx)包覆著鎳氧矽化物(Ni-O-Si)的非揮發性記憶體結構,我們認為在此濺鍍過程中會形成奈米點結構,氧氣扮演一個不可或缺的角色,可以簡單並均勻地形成高密度(~1012 cm-2)的奈米點分佈。我們同時也提出室溫下在氬氣和氮氣(Ar/N2)的環境中濺鍍混合鈀材Ni0.3Si0.7來形成鎳矽氮化物(Ni-Si-N)奈米點,結果也可發現高密度鎳矽氮化物奈米點被包覆在氮化矽(SiNx)中,並且擁有更好的儲存能力。因此我們利用這些元素之間的不同吉布斯自由能(Gibbs free energy)來產生一個內部競爭機制,可以在較低溫的環境中形成所謂的低溫化的非揮發性金屬奈米點記憶體。 我們進一步利用一個500°C~600°C的快速熱退火製程,藉由鎳與矽的化合反應來增進奈米點的結晶性(Crystallization),矽化鎳(NiSi)金屬奈米點會因此形成並且擁有較高的態位密度(Density of state)來儲存電荷並增加記憶窗口與儲存電荷穩定性;因為熱退火處理也可以改善氮化矽本身的品質與減少奈米點周圍氮化矽中的淺層缺陷(漏電路徑),記憶體的可靠度同時也被有效率地改善。因此我們成功地製作出一個具有SONOS性質的金屬奈米點記憶體,此外,根據奈米點埋藏於不同介電層中的電場結構模擬,與氧化矽包覆的金屬奈米點相較之下,由於不同介電質中具有不同的電場分佈,氮化矽包覆奈米點作為電荷儲存層有較佳的可靠度表現。最後我們製作多層的矽化鎳奈米點記憶體結構並探討其特性,發現多層奈米點比單層奈米點不僅在室溫下且在高溫時也擁有較好的電荷儲存能力和保存能力,此乃因為多層奈米點的第一與第二層因尺寸所產生的量子侷限效應(Quantum confinement effect),可以加以阻擋第三層的主要儲除電荷的流失路徑。 再者,針對介電質奈米點記憶體,我們也使用濺鍍系統形成錳矽氧化物(MnSiOx)奈米點,且進一步利用X光光電能譜(XPS)鑑別錳矽氧化物奈米點的組成以及能隙與能帶圖的建立。並藉由量測電流密度與溫度的關係,使用缺陷輔助穿隧模型來萃取錳矽氧化物的缺陷深度與密度,進而可以發覺氧原子的摻雜濃度會影響缺陷深度,使得電荷保持能力會有所差別。我們也製作雙層錳矽氧化物(MnSiOx)奈米點記憶體結構並探討其特性,可以發覺其比單層的介電層奈米點有較好的電荷儲存特性與保持能力,此乃因為介電層奈米點的電荷儲存方式是藉由自身的缺陷捕獲所致,所以已被捕獲的電荷必須先克服介電質奈米點的缺陷能障,方能逃脫出奈米點並流失掉。最後,我們所提出的奈米點結構與製造技術都可以應用於非揮性奈米點記憶體的製程技術同時也適用於現階段積體電路製程。
Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for next-generation NVM application. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. Nanocrystals (NCs) NVMs are one of promising candidates to substitute for conventional floating gate memory, because the discrete storage nodes as the charge storage media have been effectively improve data retention for the scaling down device. In this thesis, we propose three kinds of NCs with different properties (Ge, NiSi and MnSiO NCs) to overcome the limitation of conventional NVMs during the scaling down process. First, we proposed a SiGeO stacking structure serving as Ge NCs self-assembled layer for application of NCs NVMs. We successfully incorporated the oxygen atoms into SiGe layer to form a SiGeO ternary film by sputtering a commixed Si0.5Ge0.5 target in an Ar/O2 ambiance at room temperature. In this work, we fond out that pre-annealing-capping oxide (PACO) is a critical step in our experimental process, and the charge storage layer can be used the different oxidized competition mechanism between Si and Ge to form Ge NCs embedded in oxide. Hence, a uniform and high density (~1012cm-2) of Ge NCs was fabricated after a rapid thermal annealing (RTA) process. Our propose technique compared with traditional Ge NCs process can be efficiently to prevent the over-oxidation phenomenon of Ge NCs which reduces the charge trapping ability. Furthermore, we also used this similar method that oxygen was replaced by nitrogen to form the Ge NCs embedded in SiNx structure. The memory window for the stacked structure with Ge NCs embedded in SiNx layer was larger than Ge NCs embedded in SiOx layer, due to the extra charge trapping centers generated from the surrounding dielectric of Ge NCs. To compare these Ge NCs structures, we found that the Ge NCs embedded in nitride had better charge storage ability and reliability for NVM characteristics, because the nitride layer can uniformly distribute the stored charge to reduce Coulomb repulsive force effect under retention test. In recent years, most methods of NCs fabrication generally need the thermal treatment with high temperature and long duration. This procedure will influence thermal budget and throughput for the current manufacture technology of semiconductor industries. Hence, an ease and low temperature fabrication technique of Ni-O-Si and Ni-Si-N NCs was demonstrated for NVM application in this thesis. The NVM structure of Ni-O-Si NCs embedded in the SiOx layer was fabricated by sputtering a commixed target (Ni0.3Si0.7) in an Ar/O2 environment at room temperature. It can be considered that the oxygen plays a critical role during sputter process for the NC formation. In addition, a high density (~1012 cm-2) NCs also can be simple and uniform to be fabricated in our study. We also proposed a formation of Ni-Si-N NCs by replacing O2 by N2 environment during the sputtering process. It was also found that a high density Ni-Si-N NCs was embedded in the silicon nitride (SiNx) which presented larger memory effect. Therefore, by using this internal competition mechanism of charge trapping layer for these elements (Ni, Si, and O/N), we can obtain a metallic NCs NVM with low temperature process. A RTA process with temperatures about 500 and 600 °C at short duration was further used to improve the crystalline quality of metallic NCs and its memory reliability. Thermal treatment can efficiently reduce the defects (leakage path) in the SiNx which surrounds the nanocrystal. The charge storage layer of NCs embedded in SiNx shows larger memory window and better reliability over NCs embedded in SiOx, due to different distributions of electronic field in the NC and surrounding dielectric by the simulation results. In addition, multi-layer NiSi NCs NVM structure had better charge storage and retention over than single-layer metal nanocrystals under high temperature test, because of the first and second layer of multi-layer with Quantum confinement effect depended by the NC size. For dielectric NCs NVMs, we also used the sputter system to fabricate the manganese silicate (MnSiOx) NCs. The XPS results of charge trapping layer can be identified the chemical state of NCs and built the energy band diagram of our produced MnSiOx thin film. Moreover, by the relationship of current density with temperature, the trap assisted tunneling model can be used to extract the charge trapping level and density of MnSiOx. In the experiment results, the oxygen doping concentration will affect the trap level positions and also influence the retention presentations for the reliability test. Moreover, double layer MnSiOx NCs NVM also was fabricated and discussed its NVM effect. The double layer was better trapping and keeping charges ability than single layer because the trapped charges must overcome the trap barrier and then escape from NCs due to the trapping mode of dielectric NCs.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311529
http://hdl.handle.net/11536/78000
Appears in Collections:Thesis


Files in This Item:

  1. 152901.pdf