Low k Barrier All-in-one Etch Study of Copper Dual Damascene Process
Dr. Chia-Fu Chen
|關鍵字:||低介電阻障層;銅雙鑲嵌製程;Barrier;Copper Dual Damascene|
All-in-one技術在同一個清潔模式的腔體中，整合了溝槽蝕刻、去光阻及阻障層去除等步驟。這個方式也同時解決了一些阻障層去除步驟之後的製程問題。本篇論文提供的實驗結果，是關於在去光阻及阻障層去除的製程整合所遇到的問題，包括銅氧化物引起的損害銅導致電性失效、 損害銅與銅質阻障種晶層過差的附著力。為了減少損害銅導致的失效並提供更好的解決方案，可以藉著考慮整合製程步驟以及修改製程程式。實驗的程序主要是藉著兩個階段，包括控擋晶圓以及圖案晶圓的實驗; 接著是電性晶圓的實驗。這裡將討論一些不同氣體組合的製程趨勢及蝕刻後處理的步驟，進而驗證這個製程方式是有效的。|
In the era of deep submicron semiconductor fabrication, interconnection resistance-capacitance (RC) time delay dominates the performance of whole integrated circuits (ICs). To mitigate the issue, two realistic methods are accepted popularly. The first method is to replace the aluminum wires with copper interconnects which offer lower resistivity. The second method is to use a lower dielectric constant material as the inter-metal dielectric (IMD). However, the integration of such material has encounter enormous problem in mass production. When the low-k material without middle stop layer was introduced, the dual damascene processes present unique challenges of etch depth control, etch profile, striation and faceting. As a result, people struggled to align an integrated process flow to reduce the cost of production and to simplify the process flow without any impact on chip performance. Therefore , the all-in-one process was developed to meet low cost and high productivity requirement. The all-in-one process was integrated trench etch step , strip step and barrier removal step into only one clean mode chamber. Meanwhile, some process issue after barrier removal step will also be solved. This paper will present experimental results of the process development that had been carried out for trench etch with integrated strip and barrier removal process and some various issues, like copper damage by oxidized copper residue leading to electrical failure , poor adhesion between damaged surface and barrier seed layer . To reduce the copper damage induced failures and provide the better solution, recipes can be modified and the process step procedures are considered. The experiment procedures will mainly be finished by two phases. First , there are some tests for blanket wafers results and physical results. Secondary, the experiment will optimize process on electric test to meet the process acceptable specifications. Then some process trends will be discussed by different gas combinations and some post etch treatment then prove the process approach is evaluated to be workable.
|Appears in Collections:||Thesis|