Study of Nano-scale Copper Metallization on Damascene Process Integration for Semiconductor Integrated Circuits
|摘要:||隨著積體電路的進步，元件的導線(interconnection)已經進入奈米化(nano-scale)，其主要的目的在於降低積體電路高度的元件積集度產生的功率消耗與熱量，並大幅縮小其體積，達成元件輕薄短小與高功能的可能。然在這奈米化的導線過程，製程技術更由原本的鋁導線與矽氧化物的介電材料，改變成為銅導線與低介電常數(low-K)介電材料，以降低電阻-電容延遲時間效應(RC delay time effect)。
在銅導線的製造技術中，導入了的鑲嵌技術(damascene technology)成為主流，主要是因銅的蝕刻技術較難產生金屬揮發物與其銅的活性高，而將原先鋁導線技術中先由金屬圖案產生，再覆蓋介電層的步驟，改變成介電層圖案先產生，再鑲嵌入銅金屬於導線圖案中；然這鑲嵌技術涉及三個重要製程技術，分別為銅阻障層與導電功能的銅晶種層沉積(deposition for barrier and seed layers)，銅電鍍(copper electrodeposition, ECD)，銅化學機械研磨(copper chemical mechanical planarization, CMP)等技術。尤其在奈米化導線的製造技術，更是產生許多如技術整合效應、導線堆積精準與缺陷等問題，因此本論文冀以主要探討銅製程技術奈米化所需要的解決問題與製備上的策略，以達成奈米化導線的製程需求；至於低介電常數(low-K)的製程技術亦屬相當重要，將不列入本論文討論的範疇內。
就奈米化製造技術的觀點來看，銅阻障層與銅導電的晶種層沉積技術將改變原先的物理氣相沉積(physic vapor deposition, PVD)的方法，導入複雜的沉積與再濺鍍(resputter)的結合製程，或改以金屬的化學氣相沉積(chemical vapor deposition, CVD)方法，因此本論文將分別第四章節加以探討研究此製程技術的問題。另外，銅電鍍的奈米製程技術亦屬高難度的製造技術，主要不僅需達成銅的超填充(superfilling)能力，並更需達成無缺陷(defect)與空洞(void)殘留於導線中，因奈米化的導線需要控制導線的沉積奈米厚度效應與銅晶格大小，以達成低阻值與高可靠度(reliability)的導線，本論文將以第五章節加以探討研究此製程技術。
一般而言，銅的化學機械研磨技術最不成熟，其因不僅需克服研磨產成的淺碟效應(dishing effect)，更需挑戰研磨速率的精準與可靠性，因此本論文第六章節導入新的研磨漿(slurry)製造觀念;此新的研磨漿以添加抑制劑當作研磨的緩衝劑，不同於原傳統研磨漿只有氧化劑和表面活性劑，抑制劑構以長鏈碳化物當作研磨顆粒與銅不平整表面的緩衝，加速平坦化，以貢獻與突破製程技術奈米化的困難。此外，更加以探討與數學模擬其此研磨漿所帶來銅化學機械研磨技術產生的非線性關係( non-linear or non-Preston’s phenomena)，與其研磨機制。進而討論多種商業化研磨設備機構的模擬控制方法，以求製程最適化與與降低研磨製程缺陷的產生。
最後，我們以第七與第八章節加以分析銅導線製程整合的問題，如奈米化後所遇的導線圖案密度效應(pattern density effect)影響電鍍製程變異，與製程可靠度問題。並加以推導可能的機制，與提出可能的解決方法。|
With semiconductor manufacture shrunk down to the 100 nm technology, the interconnection of the device would be faced to the nano-scale manufacturing and integration. The nano-scale interconnection could reduce the high power consumption and heat accumulation, even shrink the chip volume and device sizes. The nano-scale technology and manufacture for interconnection would be induced with the copper and low-K dielectric materials, instead of the original aluminum and silicon oxide materials. Copper manufacturing technology has been developed with damascene process. It would be the key method for the copper metallization, due to the copper etching suffered with the low vaporization capability and its high chemical activity. The process would be changed from the original metal pattern defined first then dielectric oxide deposition to the dielectric oxide etching then copper metal deposition. This change involved three major key process introductions, such as the barrier and copper seeding deposition, copper electrodeposition (ECD), and copper chemical mechanical planarization (CMP) processes. Especially for the nano-scale manufacturing, the processes would be challenged with the process integration, precise interconnection alignment in lithography, process defect management issues and so on. This thesis would be focused on the copper interconnection manufacturing issues and skills for the requirements of the nano-scale interconnect. Besides, we will not focus on the low-K material introduction and integration in the damascene process, due to this big topic and subject being separated into the other discussion and theme. From the view of the nano-scale interconnection manufacture, the barrier and seeding deposition would be changed from the original convectional physical vapor deposition (PVD) methodology to the combination technology of the sputter and resputter processes or the chemical vapor deposition (CVD) methodology for copper metallization. In this thesis, we will discuss these technology and process for the nano-scale issues. Besides, the copper electrodeposition is another key process for the nano-scale interconnection. It is necessary for the nano-scale plating to achieve the super-filling in the damascene features without any defects and voids in the interconnection. Hence, the process would be mainly discussed with the overpotenital effect from the thinner seeding layer and controlled with the copper grain size distributions. Theses discussions and integration will be described in the chapter 5. Furthermore, the copper CMP process is the most key and difficult process in the copper metallization, due to its immature process integration and manufacture. Besides, the copper CMP needs to be challenged with the dishing effect and the precise process control of the polishing removal rate. Then, we introduce and develop a novel slurry with the passivation concept to overcome the difficulties of the nano-scale planarization. This passivation type of the slurry is composed of the long-chain carbon structure to act as a buffer between the abrasives and the unsmooth topology of the copper. In chapter 6, we also discuss the phenomena of non-linear or non-Preston’s polishing behavior from this slurry and understand its mechanism through simulation. The polishing kinetics and simulation on commercial polishing platforms had been studied in this chapter to reduce the defect and resolve the process control issue. Finally, we discuss the issues of the process integration and reliability in chapters 7 and 8. The integration and reliability issue would be focused on the pattern density effect on the process manufacture and its reliability problem. We present the mechanism and the solution of these issues for further improvement of the manufacture qualities.
|Appears in Collections:||Thesis|