標題: A Decorrelating Design-for-Digital-Testability Scheme for Sigma - Delta Modulators
作者: Hong, Hao-Chiao
Liang, Sheng-Chuan
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: Analog digital conversion;built-in self-test (BIST);CMOS mixed-mode circuits;design-for-testability (DFT);integrated-circuit testing;sigma-delta modulation
公開日期: 1-一月-2009
摘要: This paper presents a novel decorrelating design-for-digital-testability (D(3)T) scheme for Sigma - Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma - Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than - 5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D(3)T scheme has the potential to test moderate nonlinearity. The proposed D(3)T scheme has the advantages or achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.
URI: http://dx.doi.org/10.1109/TCSI.2008.926986
http://hdl.handle.net/11536/7787
ISSN: 1549-8328
DOI: 10.1109/TCSI.2008.926986
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 56
Issue: 1
起始頁: 60
結束頁: 73
顯示於類別:期刊論文


文件中的檔案:

  1. 000263297800006.pdf