標題: A 45nm dual-port SRAM with write and read capability enhancement at low voltage
作者: Wang, D. P.
Lia, H. J.
Yamauchi, H.
Chen, Y. H.
Lin, Y. L.
Lin, S. H.
Liu, D. C.
Chang, H. C.
Hwang, W.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2007
摘要: This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.
URI: http://hdl.handle.net/11536/7767
http://dx.doi.org/10.1109/SOCC.2007.4545460
ISBN: 978-1-4244-1592-2
DOI: 10.1109/SOCC.2007.4545460
期刊: 20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
起始頁: 211
結束頁: 214
顯示於類別:會議論文


文件中的檔案:

  1. 000257572200048.pdf