標題: 適用於高低壓共容輸入輸出介面之積體電路靜電放電防護設計
ESD PROTECTION DESIGNS FOR MIXED-VOLTAGE I/O INTERFACES IN CMOS INTEGRATED CIRCUITS
作者: 林昆賢
Kun-Hsien Lin
柯明道
Ming-Dou Ker
電子研究所
關鍵字: 靜電放電;靜電放電防護設計;高低壓共容輸入輸出介面;ESD;ESD Protection Design;Mixed-Voltage I/O Interface
公開日期: 2004
摘要: 適用於高低壓共容輸入輸出介面(Mixed-Voltage I/O Interfaces)或具有省電模式(Power-Down-Mode)功能之互補式金氧半積體電路(CMOS ICs)將使得靜電放電(Electrostatic Discharge, ESD)防護設計有更多的限制與困難。適用於高低壓共容輸入輸出介面之積體電路,靜電放電防護設計必需考慮在電路正常操作下,閘極氧化層(Gate Oxide)的可靠度問題與避免額外的漏電流路徑;而具有省電模式功能之積體電路,靜電放電防護設計必需考慮在省電模式操作下,避免額外的漏電流路徑與內部電路誤動作的發生。在靜電放電發生時,靜電放電防護電路必需能夠有效地保護內部電路防止內部電路受到損傷。此外,在高壓互補式金氧半製程技術中,靜電放電防護元件的低持有電壓(Holding Voltage)特性將使得高壓積體電路發生閉鎖效應(Latchup)或類似閉鎖效應(Latchup-Like)的危險。此問題將使得高壓積體電路之靜電放電防護設計更加困難。另一方面,在奈米互補式金氧半製程技術中,如何設計具較快導通速度且較小佈局面積的電源間靜電放電箝制電路(Power-Rail ESD Clamp Circuit)來保護超薄的閘極氧化層以應用在系統單晶片(SOC)將是個挑戰。本論文將針對高低壓共容輸入輸出介面、具有省電模式功能、高壓互補式金氧半製程技術、與奈米互補式金氧半製程技術之積體電路靜電放電防護設計上的限制與困難作討論,並進一步設計出有效的靜電放電防護電路在各相關應用之積體電路晶片。 為了提供有效的靜電放電防護於高低壓共容輸入輸出電路,本論文提出利用基體觸發(Substrate Triggered)技術來提昇堆疊電晶體(Stacked-NMOS)的靜電放電防護能力。利用基體觸發技術可使得堆疊電晶體的觸發電壓(Trigger Voltage)降低,如此更能有效地保護高低壓共容輸入輸出電路。這種利用基體觸發技術所設計靜電放電防護電路其製程步驟完全相容於一般互補式金氧半導體的製程,且不需要使用厚的閘極氧化層。適用於2.5V/3.3V共容高低壓輸入輸出電路的靜電放電防護電路已在0.25微米互補式金氧半製程中實際被製作與驗證。實驗結果顯示利用基體觸發技術所設計靜電放電防護電路可使得堆疊電晶體的觸發電壓從8.5 V降低到5.3 V;而高低壓共容輸入輸出電路在240微米總寬度的堆疊電晶體條件下,其人體放電模式(Human-Body-Model, HBM)的靜電放電耐受能力可以從原來的3.4 kV提昇到5.6 kV。 為了提供有效的靜電放電防護於具有省電模式功能之積體電路晶片,本論文提出新型的靜電放電防護電路架構。此靜電放電防護電路架構包括一靜電放電匯流排(ESD Bus)與數個二極體(Diode),使得積體電路進入省電模式操作下,可避免從輸入輸出焊墊(I/O Pad)到VDD電源線間的漏電流路徑及內部電路誤動作的發生。當積體電路在正常操作下,此設計具有極低的漏電流且不會影響到內部電路的正常工作。在此靜電放電防護電路架構中,VDD到VSS電源間以及靜電放電匯流排到VSS電源間,各有一組靜電放電箝制電路以達到全晶片靜電放電防護設計的目的。在0.35微米互補式金氧半製程中,此設計可達到7.5 kV的人體放電模式靜電放電耐受能力。此外,在此靜電放電防護電路架構中,本論文也提出了改善輸出端電壓準位的電路,使得內部電路在正常操作下輸出端的最高電壓可以達到VDD的電壓準位。 在高壓互補式金氧半製程技術中,金氧半場效電晶體(MOSFET)、矽控整流器(SCR)或者是雙載子電晶體(BJT),被廣泛的用作靜電放電防護元件。但是這些靜電放電防護元件在驟回崩潰(Snapback Breakdown)狀態下的持有電壓都遠小於高壓Vcc電源的電壓。此低持有電壓的元件特性將使得在實際系統應用下,高壓積體電路發生閉鎖效應或類似閉鎖效應的危險,尤其是將這些元件用作電源間靜電放電箝制元件。本論文針對此問題作深入的研究,並進一步提出新型的電源間靜電放電箝制電路以避免高壓積體電路發生閉鎖效應或類似閉鎖效應的危險。此設計是藉由調整堆疊元件的數目,使得堆疊元件結構在驟迴崩潰狀態下的箝制電壓超過高壓Vcc電源的電壓。如此,在不需要增加或改變製程步驟下,便可以達到避免高壓積體電路發生閉鎖效應或類似閉鎖效應的目的。利用此概念設計的堆疊場氧化層電晶體結構(Stacked Field-Oxide Structure)用在電源間靜電放電箝制電路已經在供應電壓為40 V的0.25微米互補式金氧半製程中驗證,其能有效地防止高壓積體電路發生閉鎖效應或類似閉鎖效應的危險。 為了在奈米金氧半製程技術中實現具較高靜電放電耐受能力且較小佈局面積的輸入輸出單元(I/O Cell),本論文在0.13微米互補式金氧半製程中,提出使用電源間寄生矽控整流器來作為電源間靜電放電箝制元件的輸入輸出單元。本論文共提出兩種寄生矽控整流器結構,其在電路正常操作下並沒有閉鎖效應的問題。在佈局上,此寄生矽控整流器結構是放置於輸入輸出單元的輸入(或輸出)P型電晶體與N型電晶體之間。此外,寄生矽控整流器的導通速度可經由基體觸發技術而明顯的提昇。在0.13微米互補式金氧半製程中,此設計可達到5 kV的人體放電模式靜電放電耐受能力。此設計讓每個輸入輸出單元都具有一個快導通速度且高靜電放電耐受能力的電源間靜電放電箝制元件,因此在單一的輸入輸出單元便可以提供全晶片靜電放電防護所需之放電路徑。利用此設計,晶片可在較小的佈局面積下具有更高的靜電放電耐受能力。 在本博士論文中,已經針對高低壓共容輸入輸出介面、具有省電模式功能、高壓互補式金氧半製程技術、與奈米互補式金氧半製程技術等應用之積體電路設計出高效能的靜電放電防護電路。所設計的靜電放電防護電路均已在實際晶片上成功驗證,並有相對應的國際期刊論文發表與專利申請。
For the CMOS integrated circuits (ICs) with the mixed-voltage I/O interfaces or power-down-mode application, the on-chip electrostatic discharge (ESD) protection circuits will meet more design constraints and difficulties. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths during normal circuit operating operation, whereas that for IC with power-down-mode operation should avoid the undesired leakage current paths and malfunction during power-down-mode operation. During ESD stress condition, the on-chip ESD protection circuit should provide effective ESD protection for the internal circuits. In high-voltage CMOS technology, the low-holding-voltage characteristic of ESD protection devices has been found to cause the high-voltage CMOS ICs susceptible to latchup or latchup-like danger during normal circuit operating condition. How to avoid the latchup or latchup-like failure in high-voltage CMOS ICs will be an important challenge to on-chip ESD protection design for high-voltage CMOS IC products. In nanoscale CMOS technology, how to realize the turn-on-efficient and area-efficient power-rail ESD clamp circuit to protect the ultra-thin gate oxide will be an important challenge to system-on-a-chip (SOC) applications with a much larger chip size. In this thesis, the ESD design constraints in mixed-voltage I/O interfaces, power-down-mode application, high-voltage CMOS technology, and nanoscale CMOS technology are presented. Furthermore, the novel on-chip ESD protection circuits have been developed to overcome the design constraints in such applications. To provide effective ESD protection in the mixed-voltage I/O interfaces, a new ESD protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to reduce the trigger voltage of the stacked-nMOS device for ensuring effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5V/3.3V-tolerant mixed-voltage I/O circuit in a 0.25-µm salicided CMOS process. By using this substrate-triggered design, the trigger voltage of the stacked-nMOS device can be reduced from the original 8.5V to become 5.3V to ensure effective protection for the mixed-voltage I/O circuits. The human-body-model (HBM) ESD level of the mixed-voltage I/O buffer with a stacked-nMOS of 240-µm channel width can be improved from the original 3.4 kV up to 5.6 kV by this substrate-triggered circuit. To provide effective ESD protection for power-down-mode application, a new design on the ESD protection schemes for CMOS IC operating in power-down-mode condition is proposed. By using an additional ESD bus and diodes, the new proposed ESD protection schemes can block the leakage current from I/O pad to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the new proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and VDD ESD bus line. Experimental results have verified that the HBM ESD level of the new schemes can be greater than 7.5kV in a 0.35-µm silicided CMOS process. Furthermore, the output signal of the proposed ESD protection schemes can be successfully pulled up to VDD again by the output-swing improvement circuit under normal circuit operating condition. In high-voltage CMOS technology, high-voltage MOSFET, silicon controlled rectifier (SCR) device, and bipolar junction transistors have been widely used as on-chip ESD protection devices. The double snapback characteristic in the high-voltage nMOSFETs has been investigated and analyzed by both measured and simulation results. Furthermore, the holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the high-voltage power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup or latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuits between the high-voltage power lines. In this thesis, the latchup or latchup-like issues in high-voltage CMOS ICs have been investigated in details. By adjusting different numbers or different types of stacked ESD devices in the power-rail ESD clamp circuits, the total holding voltage of the stacked structure can be designed higher than the high-voltage supply voltage without using extra process modification in the high-voltage CMOS technology. A new latchup-free design on the high-voltage power-rail ESD clamp circuit with stacked field-oxide structure is proposed and successfully verified in a 0.25-µm 40-V CMOS process to achieve the desired ESD level. Therefore, latchup or latchup-like issues can be avoided by stacked field-oxide structures for the IC applications with power supply of 40V. In order to realize the high-ESD-robust and high-area-efficient I/O cells in nanoscale CMOS technology, a new ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in a 130-nm CMOS process is proposed. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the HBM ESD level of this new proposed I/O cells can be greater than 5kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of I/O cell. Such I/O cells are very suitable for SOC applications in nanoscale CMOS technology. In summary, the novel ESD protection designs have been successfully developed for mixed-voltage I/O interfaces, power-down-mode application, high-voltage CMOS technology, and nanoscale CMOS technology with high ESD robustness. Each of the proposed ESD protection circuits has been practically verified in the silicon testchips.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008911845
http://hdl.handle.net/11536/77001
Appears in Collections:Thesis


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