標題: 複晶矽薄膜電晶體中漏電流及可靠度課題之研究
A Study of Leakage Current and Reliability Issues in Poly-Si Thin-Film Transistors
作者: 李明賢
Ming-Hsien Lee
林鴻志
黃調元
Horng-Chih Lin
Tiao-Yuan Huang
電子研究所
關鍵字: 薄膜電晶體;複晶矽;奈米線;自我對準;閘極引發汲極漏電流;電漿處理;矽鍺;快速熱退火;熱載子;熱載子衰退;熱載子效應;測試結構;交流施壓;能態密度;元件模擬;可靠度;Thin-film transistor;Polycrystalline silicon;Nanowire;Self-aligned;Gate-induced drain leakage (GIDL);Plasma treatment;Silicon germanium;Rapid-thermal annealing (RTA);Hot-carrier;Hot-carrier degradation;Hot-carrier effect;Test structure;AC stress;Density of states;Device simulation;Reliability
公開日期: 2006
摘要: 本論文提出並實作一種具有自我對準能力之複晶矽奈米線薄膜電晶體,以及一種應用於解析熱載子衰退的新穎測試結構。首先,我們描述奈米線薄膜電晶體之製程,及如何製作此複晶矽奈米線的製程參數。我們也審視了影響奈米線尺寸及形狀之因子。這個製程非常簡單,不牽涉到複雜且昂貴的電子束微影或是深紫外光微影設備。 我們研究並討論了奈米線薄膜電晶體的開狀態特性,包括剛製成的元件及經過電漿處理的元件,然後討論了電漿處理及尺寸對於電特性的影響。與傳統平面結構的元件比較,此奈米線通道的優點包括有:絕佳的開電流密度及對短通道效應有較佳的控制能力等等。此外,由於奈米線的寬度很窄,在進行氫化的時候能夠更夠效率地使元件的特性改善。 我們也研究了奈米線薄膜電晶體其獨特的關狀態漏電流機制。產生於閘極與汲極間重疊區域的閘極引發汲極漏電流(gate-induced drain leakage, GIDL),被發現是造成此一異常漏電流的元兇。我們仔細檢驗了此一異常漏電流的產生原因,以及電漿處理對於此漏電流的影響。我們發現此一電流起因於在閘極與汲極介面的低掺雜區域,此區域引發了一條額外的漏電流路徑。在檢驗了漏電流的起因之後,我們提出並實際驗證了數種減少此一漏電流的方案。這些方案包括了快速熱退火(Rapid thermal annealing, RTA)、在閘極與汲極間插入一層氮化矽、以及改使用複晶矽鍺材料作為奈米線通道等。這數種方案的特色被逐一比較並加以討論。 我們也提出並實作了一種新穎的測試結構,可以解析薄膜電晶體中熱載子衰退所發生的位置及時間演變。此一新穎測試結構的製作方式與傳統的薄膜電晶體一樣容易,與現在的超大規模積體電路製程完全相容,並且不需要額外的光罩。我們檢視了此一測試元件所帶來之靈敏度的提昇以及在決定施壓條件時的優點,也探討了金屬後電漿處理對於熱載子衰退效應的影響。特別的是,我們在研究過程中,利用此一結構發現了兩種會造成臨界電壓漂移的機制。 由於此測試結構的高靈敏度及解析能力,使得在研究可靠度相關議題時,能夠直接利用此一測試結構直接觀察元件的衰退現象,不必再利用高電壓施壓條件下的結果,去推測元件在正常操作或是低電壓施壓條件之下的衰退現象,並可以比較元件在高低電壓施壓下的不同現象和機制。 我們也利用此一測試結構,研究了當元件操作於交流模式時,所產生的熱載子衰退現象。關於操作頻率、上升及下降時間都有詳細的探討。利用此一測試結構的特性,輸入訊號中各個準位階段其所對應到的損傷位置可以被定位出來。實驗結果顯示,損傷主要是當閘極訊號切換時,瞬間所產生的熱載子所導致。伴隨著偵測熱載子衰退時的高靈敏度,此一元件也可以應用於一般交流操作時的可靠度研究之用。 在此論文的最後一個部份,我們進行了關於缺陷能態密度的分析。在說明原理及方式之後,我們可以利用前述的測試元件萃取出當元件受到熱載子損傷之後,其能態密度分佈的變化。由於傳統元件在受到熱載子損傷後,通道中各部位的能態密度分佈將會變得不均勻,且局部的缺陷密度增加量將會在萃取能態密度分佈時被整體所稀釋,造成實務上萃取的困難。利用此一測試元件,我們可以萃取出各部位其能態密度分佈的變化,並重組成元件衰退後的真實分佈狀態,並利用元件模擬技術重現元件的次臨界特性曲線。
In this thesis, we proposed and demonstrated a poly-Si thin-film transistor with self-aligned nanowire channels, as well as a novel test structure suitable for resolving hot-carrier degradation. Firstly, the fabrication of proposed NWTFT was described, followed by the detail in poly-Si nanowire formation and investigation of the factors affecting size and shape of the nanowire. The fabrication is simple and does not involve costly lithography tools. On-state characteristics of NWTFT were then examined and discussed, including as-fabircated and plasma-treated samples. The effects of post-metal treatment and geometric parameters on NWTFT were then discussed. The advantages of NWTFT were demonstrated by comparing with traditional planar structures. Such nanowire structure has been shown to be excellent in terms of on-current per unit width and controllability over short-channel effects. Owing to the fine nano-scale of NW width, hydrogenation would be very efficient for further performance improvement. The unique off-state leakage mechanism of NWTFT was also investigated. A gate-induced drain leakage (GIDL), which is generated in the overlapped region between the gate and the drain, was uncovered as the major culprit for the anomalous leakage. The origin of the anomalous leakage was then examined, as well as the effect of post-metal treatment. This current was found to originate from the lightly-doped region at gate/drain interface, which induced an additional current path. After that, several modifications were proposed and demonstrated in order to alleviate the unique leakage. Rapid thermal annealing (RTA), inserted nitride mask, and poly Si1-XGeX were investigated and compared. A tester, which can spatially and temporally resolve hot-carrier degradations, was proposed and demonstrated. The fabrication of the novel test structure is simple and compatible with standard ULSI processings without extra masking. Advantages in sensitivity and stress-condition determination were discussed, accompanying with the effects of post-metal plasma treatment on hot-carrier degradations. Specifically, we found that at least two mechanisms are responsible for the negative threshold voltage shift detected by monitor transistors. The high sensitivity and resolving capability of the novel test structure can also help researchers observe directly degradation phenomena occurring when devices are stressed under moderate or minor conditions. We also studied the phenomena of hot-carrier degradation during AC operations using the proposed test structure. Effects of frequency, rising and falling times, were investigated and discussed. The phenomena of the hot-carrier degradation can be spatially resolved using the proposed tester. By applying such a tester to AC hot-carrier stressing, the relationship between different stages of input signal and resultant damage location can be established. The tester also showed a high sensitivity in detecting even mild AC degradation. The experiment provides unambiguous evidence that the damage occurs during the transient stages, with the aid of the test structure. At the last part of the thesis, the analyses related to effective density-of-states distributions were performed. After the description of experimential procedures, effective density-of-states distributions of localized damaged regions were extracted using the aforementioned tester. The information revealed by the analyses was then discussed. The extracted density-of-states distributions for both unstressed and stressed films were used to conduct simulations for subthreshold characteristics of TFTs and compared with the experimental data. The combination of the proposed novel test structure and density-of-states extraction technique provides a powerful tool for resolving the non-uniform density-of-states distribution of TFTs after HC stressing, which is impossible using traditional testers.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008911576
http://hdl.handle.net/11536/76735
Appears in Collections:Thesis


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  1. 157601.pdf
  2. 157602.pdf
  3. 157603.pdf