標題: 前瞻非揮發性記憶體元件之研究
Study on Advanced Nonvolatile Memory Devices
作者: 顏碩廷
Shuo-Ting Yan
施敏
張鼎張
Simon M. Sze
Tinn-Chang Chang
電子研究所
關鍵字: 非揮發性記憶體;奈米晶體;快閃記憶體;Nonvolitle memory device;nanocrystal;flash memory
公開日期: 2003
摘要: 首先,在SONOS非揮發性記憶體的研究方面,本論文利用高密度電漿化學氣相沈積製作含有多能阱(trap)之載子儲存氮化矽層或其他介電質。由於高密度電漿化學氣相沈積薄膜,於沈積過程中具有較高的離子轟擊效應,導致形成的薄膜較緻密且斷鍵陷阱(trap)較多,對電子的捕獲效應較佳,期望達到較大的記憶窗,以改善記憶體元件的保存時間。高密度電漿氮化矽薄膜比傳統低壓化學氣相沉積氮化矽,具有較大的記憶窗口。由複立葉轉換紅外線光譜圖可以發現,高密度電漿氮化矽薄膜由於含有許多N-H鍵結作為載子捕獲的陷阱,證明其記憶窗口較大的原因。在電流-電壓特性方面,雖然高密度電漿能阱比傳統低壓化學氣相沉積氮化矽多,但漏電特性比較起來,僅大不到一個因次,另外儲存載子在高溫150度下的保存時間亦說明了高密度電漿氮化矽SONOS記憶體元件的可靠性。 此外,我們更針對傳統ONO結構的製程方式加以改善,例如在穿隧氧化層上方沉積高密度電漿氮化矽薄膜,並加以高溫熱氧化,異於傳統利用低壓化學氣相沉積作為控制氧化層的直接沉積方式,使閘極堆疊介電層結構漏電極降低及崩潰電場提高,並獲得期望中具有較佳的介電特性及可靠性。 在載子儲存的介電層方面,除了Si3N4之外,以往的研究著重於Al2O3,TiO2,Ta2O5等,本論文更進一步地在其它的介電材料中探索,預期找到一種適合的載子儲存單元絕緣層,例如含氧碳化矽(SiC:O)薄膜,並最佳化之。利用高密度電漿薄膜直接沉積的方式,製作二氧化矽/SiC:O/二氧化矽的三明治結構。藉由含氧碳化矽對於不同氧含量的電容-電壓特性圖及電流-電壓特性圖發現,當氧含量依序漸增時,含氧碳化矽之記憶窗口大小隨氧含量的增加而變小,另外藉由氧含量的控制,可達到較大的崩潰電壓值。我們亦提出了一個物理模型,解釋含氧量較少時,崩潰電壓較大的原因。本研究欲針對材料,製程及量測分析方面加以最佳化之。 關於含氧碳化矽作為載子儲存單元的記憶體元件方面,不同於上述利用高密度電漿化學氣相沉積的方式製作,我們亦提出了利用在穿隧氧化層上之碳化矽薄膜熱氧化的方式,使碳化矽薄膜氧化為含氧碳化矽薄膜,作為載子儲存的單元,最後覆蓋二氧化矽薄膜作為控制氧化層。在碳化矽薄膜的氧化研究方面,我們發現低溫(800度)熱氧化比高溫(925度)熱氧化的含氧碳化矽,具有更高的記憶窗口,亦即具有較高的載子儲存能力。利用複利葉轉換紅外線光譜儀(FTIR)等材料分析工具,我們提出了解釋具有較高記憶窗口含氧碳化矽行為的物理模型。 傳統的浮停閘快閃記憶體是利用連續的多晶矽半導體薄膜作為載子儲存的單元;SONOS非揮發性記憶體係利用絕緣體氮化矽薄膜,作為載子儲存的單元。本論文提出了一種利用似超晶格(quasi-superlattice)結構,作為載子儲存的單元。在2-3奈米的穿隧氧化層上方,依序沉積氮化矽,非晶矽,氮化矽,非晶矽,各約1-2奈米,形成似超晶格結構,最後覆蓋氧化矽作為控制氧化層,形成非揮發性記憶體元件結構。在記憶體特性的表現上,記憶窗口有隨著寫入電壓增大而增大的趨勢,並且具有明顯的兩個起始電壓偏移抖增的現象。藉由適當的閘極電壓寫入,此元件具有每個記憶單元(memory cell)兩個位元(bit)的操作能力,只單純由閘極利用F-N穿隧寫入,而不是像SONOS元件需利用源極與汲極雙向的寫入與讀取來定義每個記憶單元的兩個位元。本論文針對此似超晶格記憶體元件,提出了一個物理模型來解釋兩個位元的儲存,並且針對閘極堆疊結構室溫及低溫的漏電效應,做了物理性的探討。 在奈米晶體非揮發性記憶體之研究方面,首先,我們成功地利用矽化鍺薄膜熱氧化研製出包覆在氧化矽中的鍺奈米點。在穿隧氧化層上方沉積矽化鍺薄膜,爾後利用高溫乾氧化,使鍺向下析出於穿隧氧化層上方,矽氧化成二氧化矽作為控制氧化層(control oxide),形成鍺奈米點包覆於二氧化矽中的結構。由穿透式電子顯微鏡可知鍺奈米點直徑大為5.5奈米,元件的記憶體特性以及可靠性也相當穩健。當上述鍺奈米點再加以過度熱氧化之後,鍺便會氧化為氧化鍺,形成氧化鍺奈米點。經由電性量測後發現,氧化鍺奈米點也確實有記憶體特性,另外經由x-ray absorption near edge spectroscopy (XANES)也證實穿透式電子顯微鏡照片中的奈米點成分為氧化鍺,我們並且提出了一個物理模型來解釋此元件之記憶體效應。 除了半導體奈米點之外,本論文亦針對金屬奈米點做深入的研究。在金屬奈米點的製作方面,首先在穿隧氧化層上方沉積矽化鎢薄膜,並覆蓋上一層非晶矽薄膜約8奈米。當試片經過高溫熱氧化之後,成分矽會氧化為二氧化矽作為控制氧化層,而矽化鎢中的金屬成分鎢會傾向向下析出,成核於穿隧氧化層上方,形成鎢奈米點,作為載子儲存的單元。在氧化的過程中,氧化參數需嚴格控制,否則金屬矽化鎢可能會氧化不足仍為薄膜,或是氧化過度將金屬鎢全部氧化。關於金屬鎢奈米點記憶體元件的記憶體特性,其具有相當大的記憶窗口(memory window)可作為定義0或1的依據,另外,此元件反覆操作的忍耐度(endurance)也可以達到一百萬次以上。
We have studied experimentally and theoretically three types of nonvolatile semiconductor memories: the SONOS, the nanocrystal/nanodot, and the quasi-superlattice memory devices. On the study of the silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory technology, high density plasma chemical vapor deposition (HDPCVD) is used to fabricate trap-rich silicon nitride or other dielectrics as the charge storage element. It is observed that the densified and trap-rich silicon nitride film from HDPCVD possesses a larger memory window than that of the conventional low pressure chemical vapor deposited (LPCVD) silicon nitride. It is found from the Fourier Transform Infrared Spectrum (FTIR) that there are N-H bonds within the HDPCVD silicon nitride as the charge trapping sites, which certifies the reason of the larger memory window. The HDPCVD silicon nitride is deposited on the tunnel oxide, followed by a high temperature oxidation process. As compared to the LPCVD deposition as the control oxide, the HDPCVD processes result in a lower leakage current and higher breakdown voltage. In addition to silicon nitride as the storage layer, we have also studied the oxide/SiC:O/oxide sandwiched structures using HDPCVD processes. From the capacitance-voltage and current-voltage characteristics of oxygen-incorporated silicon carbide with different oxygen content, it is observed that the memory window is decreased with increasing the oxygen content. By controlling the oxygen content, a higher breakdown voltage can be achieved. A physical model is proposed to explain the higher breakdown voltage with less oxygen content of the oxygen-incorporated silicon carbide. We have also studied the thermal oxidation of SiC layer on the tunnel oxide as the charge storage layer followed by control oxide capped. In the study of the oxidation of SiC, it is found that low temperature (800 ℃) oxidized SiC shows a larger memory window than that of the high temperature (925 ℃) oxidized SiC. Using the FTIR spectroscopy, a physical model is proposed to explain the behavior of low temperature oxidized SiC with larger memory window. On the study of the quasi-superlattice structure, we have sequentially deposited 1-2 nm silicon nitride and a-Si on a 2-3 nm tunnel oxide in two cycles to form the quasi-superlattice structure. Finally, SiO2 is capped as the control oxide. The memory window is increased with the programming voltage. Also, two sudden rises of the threshold voltage shift are observed. By suitably operated gate voltage, this memory device shows the capability of the operation of 2-bit per cell. The 2 bits can be operated and defined by F-N tunneling rather than the source/drain bidirectional programming and reading of the conventional SONOS memory devices. A physical model is proposed to explain the 2-bit storage and the investigation of room and low temperature leakage behavior of the gate stack is also considered. On the study of nanocrystal nonvolatile memory devices, we have successfully fabricated germanium nanocrystals embedded in silicon dioxide by the thermal oxidation of SiGe. SiGe layer is deposited on the tunnel oxide, followed by high temperature thermal oxidation. The Ge element of the SiGe layer is downward segregated and precipitated on the tunnel oxide and the Si element is oxidized into silicon dioxide as the control oxide. From the analyses of the TEM micrograph, it is observed that the size of the Ge nanocrystals is around 5.5 nm. The memory effects and the reliability of the memory are characterized robust. As the germanium nanodots are over-oxidized, the germanium nanodots are oxidized into germanium oxide dots. It is found that the germanium oxide exhibits an apparent memory effects. Also, the x-ray absorption near edge spectroscopy (XANES) analysis certifies the composition of the GeO2 nanodots in the TEM micrograph. A physical model is proposed to demonstrate the memory effects of the GeO2 memory device. In addition to semiconductor nanocrystals, metal nanodots are investigated. On the aspect of the fabrication of metal nanodots, tungsten nanodots are firstly demonstrated. The tungsten silicide layer is physically deposited on the tunnel oxide and an amorphous Si layer is capped on the silicide layer. As the sample is high temperature thermally oxidized, the silicon element is oxidized into silicon dioxide as the control oxide and the tungsten element tends to segregate downward and precipitate on the tunnel oxide. During the oxidation process, the parameters of the oxidation need to be well control or the tungsten silicide will be under-oxidized or over-oxidized. The tungsten nanocrystal memory device shows a large memory window to be defined as “1” or “0”. Also, the endurance characteristics of the memory device achieve 106 write/erase cycles which show the robustness of the memory device.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008911539
http://hdl.handle.net/11536/76702
Appears in Collections:Thesis


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