標題: 主動顯示器用低溫多晶矽薄膜電晶體之元件特性與補償電路研究
Study on Characterization and Compensation Circuits of Low-Temperature Polycrystalline Silicon Thin-film Transistor for Active Matrix Displays
作者: 盧皓彥
祁甡
張鼎張
Sien Chi
Ting-Chang Chang
光電工程學系
關鍵字: 薄膜電晶體;補償畫素設計;主動式顯示器;Thin Film Transistor;Compensation Pixel Design;Active Matrix Display
公開日期: 2007
摘要: 本論文首先提出一種具有金屬遮光層(Metal shielding layer)的新穎低溫多晶矽薄膜電晶體元件結構。於玻璃基板上先沉積一層金屬薄膜,並依序沉積緩衝層(Buffer layer)與非晶矽薄膜,再利用主動層之光罩進行一次蝕刻,如此並不會增加光罩數,此遮光層可以阻擋背光照射到多晶矽層,完全消除光漏電與次臨界擺幅(Sub-threshold swing)於背光環境下之劣化,然而,此新式結構低溫多晶矽薄膜電晶體之臨界電壓於暗態下會隨著汲極電壓而飄動,由於金屬遮光層與汲極電極互相重疊,形成一寄生電容,汲極電壓會經由此寄生電容耦合至金屬遮光層中,造成一電壓分佈於其中,進而影響元件之臨界電壓;為了消除此一問題,我們將金屬遮光層利用額外一道光罩來定義其圖案,並研究此部分金屬遮光層位於通道中央或接面區之元件特性,具有部分金屬遮光層之元件,無論遮光層位於哪一區,其臨界電壓皆不再隨汲極電壓而改變,此外,當部分金屬遮光層位於汲極接面區時,能夠有效的抑制光漏電流之大小,反之,置於源極接面區或中央通道區之部分遮光層皆無降低光漏電流之功效,然而,一旦施加大的汲極電壓,位於汲極接面之金屬遮光層其遮光效果便會減弱,我們亦根據所獲得之實驗數據提出了一合理模型來解釋此現象。 此外,我們亦嘗試對緩衝層之成分與其表面進行調變來抑制光電流的產生,本論文提出了一種可吸收光源之介電層作為緩衝層,可將大部份之背光吸收,所以多晶矽層所吸收的光強度便會減少,進而達到降低光漏電的效果,此光吸收緩衝層主要為富含矽(Si-rich)之二氧化矽層或是矽化氮層,實驗發現,富含矽介電層之光吸收能力與其薄膜厚度成正比,不論是使用富含矽之二氧化矽層或是矽化氮層來製作元件,皆可達到30%∼50%的光漏電流改善。此外,本論文亦對一般緩衝層之表面進行氨電漿(NH3 plasma)處理,利用氨電漿對緩衝層表面進行轟擊(Bombardment),使其表面裂化以產生大量之介面缺陷,此製程不僅不需要增加額外的光罩數,且可以完全相容於一般標準製程,而緩衝層表面電漿處理過之元件其基本特性與主要參數皆與標準元件相同,沒有金屬遮光層結構臨界電壓飄移的問題,如此一來,光激發出的電子-電洞隊將可透過多晶矽薄膜與緩衝層介面之缺陷密度進行複合,可有效降低光漏電與改善照光下之元件次臨界擺幅。 本論文也研究探討多晶矽薄膜電晶體元件於照光下之光漏電與次臨界擺幅增加的物理機制,首先將緩衝層利用氬離子(Argon)佈植進行表面轟擊,使多晶矽薄膜與緩衝層介面產生許多缺陷密度,我們發現經由緩衝層表面轟擊之元件,其光漏電與照光下次臨界擺幅特性具有顯著的改善,由於多晶矽薄膜吸收被光後會產生許多電子-電洞對,透過引入之缺陷密度可減少光致電子與電洞,因而造成較低的光漏電流與較佳的次臨界擺幅,此外,一種新式的測式結構亦在本論文中被提出,利用圖案化之金屬遮光層結構,我們可定義照光區於汲極或源極接面區,其中當照光區位於源極接面且施加大汲極電壓時,照光下次臨界擺幅有著顯著的上升,因此,根據此實驗結果,可推論次臨界擺幅於照光下之機制並於本論文中提出物理模型與能帶圖以解釋之。 由於多晶矽薄膜電晶體能夠整合週邊驅動電路進而由於多晶矽元件應用於面板週邊驅動邏輯電路時,需要考量到多晶矽元件可靠度的問題,本論文中亦以電容-電壓法(Capacitance-Voltage measurement)來研究低溫多晶矽薄膜電晶體於交流操作下之可靠度,研究中發現交流訊號測試會造成元件導通電流嚴重的下降,但其起始電壓變化並不大,同時汲/源極寄生電阻的也急劇增加,此外,元件劣化後之低頻電容電壓曲線無明顯變化,但高頻下之電容電壓曲線卻隨著閘極正電壓而變化,說明了多晶矽薄膜電晶體於交流操作下之劣化機制主要為淺態能階(Tail state)的增加而深態能階(Deep state)密度並無太大變化,同時透過電容電壓曲線,我們也發現交流訊號所產生之淺態能階為對稱分佈於源極與汲極。此外,具有橫向結晶之低溫多晶矽元件於交流訊號下之可靠度亦在此論文中被研究,我們可以將橫向結晶晶晶界(Grain boundary)分為主晶界(main-GB)與次晶界(sub-GB),主晶界的特徵在於其分布方向垂直元件通道,並且為一突起(Protrusion)結構;次晶界則是平行通道方向且較平坦,論文中挑選兩種較明顯對比之電晶體進行分析,GB-TFT為一含有主晶界在通道中央,NGB-TFT中則僅有次晶界存在,經過施加交流訊號測試,發現GB-TFT之劣化情形較NGB-TFT嚴重,我們量測了此兩種元件之電容電壓曲線並進行通道電場電腦模擬,發顯GB-TFT之突起結構將會造成尖端電場效應,使得此區聚集的載子較多,進而在源極與汲極兩端之高電場下造成元件的劣化。 本論文也提出了一種用於有機電激發光顯示器(AMOLED)之補償畫素電路設計,此電路設計包含了五顆低溫多晶矽薄膜電晶體與一儲存電容結構,由於低溫多晶矽薄膜電晶體其均勻度受到結晶晶界的影響,畫素之間的元件特性皆不相同,使得各畫素輸出亮度會友不均勻的情形,同時,由於金屬導線之電阻效應會造成電壓供應端(VDD)經過長距離導線時產生一電壓下降的現象,此現象亦會造成有一電激發光顯示器畫面亮度有沿著某方向遞減的情形,本論文所提出的畫素電路與新補償方法可在一次操作中同時消除元件臨界電壓飄移與電壓源下降所導致之輸出電流變動,經由HSPICE軟體的驗證,此電路設計可用於高解析度與大尺寸之有機電激發光顯示器中。 本論文最後研究提出一種利用非晶矽薄膜電晶體之有機電激發光顯示器畫素設計,由於非晶矽薄膜電晶體具有良好的元件均勻度與相當低的製造成本,非常適合做為有機電激發光顯示器之背板(Backplane),然而非晶矽薄膜電晶體之臨界電壓會隨著操作時間而上升,且有機電激發光二極體之起始電壓亦有隨著使用時間增加的趨勢,造成輸出亮度之下降,此新式非晶矽薄膜電晶體畫素設計利用源極隨耦器(Source follower)之概念,不僅結構與補償步驟簡單,並可同時補償元件臨界電壓與有機電激發光二極體起始電壓的影響,可應用於大尺寸有機電激發光顯示器。
A novel technology to eliminate the photo leakage current of poly-silicon thin film transistor (poly-Si TFT) with top gate is developed. A thin metal film is formed on the glass substrate to be used as light-shielding layer. The light-shielding layer, buffer layer and active island are patterned by employing the same mask. The leakage current and the variation of sub-threshold swing in the proposed devices are suppressed completely under illumination. Owing to the parasitic capacitance in the overlap region between the drain side and the metal shielding layer, a floating voltage coupled from drain bias would influence the threshold voltage of the proposed poly-Si TFTs. In order to solve this issue, a partial metal shielding structure for poly-Si TFT is studied. The metal shielding layer is formed and etched to be located in the channel region and junction regions. According to this structure, the shift of threshold voltage with increasing drain bias is entirely eliminated. Furthermore, the photo leakage current of poly-Si TFT with partial metal shielding layer located in the drain junction is suppressed. However, the shielding effect is vanished as the drain voltage is high. Based on these data, this study also proposes a model to explain the mechanism of partial metal shielding layer located at drain side for lowing photo leakage current. In addition, poly-Si TFT with light absorption structure is proposed to lower the photo leakage. No need of adding process steps or number of masks, the oxide film or SiNX film of buffer layer is replaced by Si-rich dielectric films. By this method, the photo leakage can be markedly lowered and the degradation of sub-threshold swing is also reduced. It is observed that the light absorption capacity of Si-rich dielectric material is strongly proportional to the film thickness. In addition, the technology of poly-Si TFTs with low photo leakage current is developed in this work. The electrical characteristics of poly-Si TFT under illumination were significantly improved employing the NH3 plasma treatment on the buffer layer, no need for complicate device structure and additional masks. The generation of trap states originated from the plasma bombardment on the interface between poly-Si layer and buffer oxide can effectively recombine the light-induced electron-hole pairs. The fewer residual electron-hole pairs in the bottom of poly-Si layer leads to the lower photo leakage current and improved sub-threshold swing, as well as also maintain the good electrical characteristics in the dark sate. Next, poly-Si TFTs with different process flows are used to investigate the electrical characteristics under illumination. First, the surface of buffer layer of poly-si TFT is degraded by Argon ion implant to generate plenty of trap densities on the interface of poly-Si layer and buffer layer. The photo leakage current and the degradation of sub-threshold swing are improved substantially, compared to the conventional poly-Si TFT. It is attributed to that the light induced electron-hole in the bottom of poly-Si film may be recombined directly via the surface state densities. Therefore, the fewer electrons and holes lead to the lower photo leakage current and less increase of sub-threshold swing, respectively. Moreover, The electrical characteristics of poly-Si TFTs with patterned metal shielding layer under illumination are investigated in this study. The location of the exposure region in poly-Si layer is well defined by employing the proposed structure. The photo leakage current increases obviously as the exposure region is located in drain junction. Therefore, the drain junction under light exposure is effective region to induce the photo leakage current. However, the sub-threshold swing of TFT under illumination is significantly degraded while the exposure region is located in source junction with high drain voltage. It is indicated that the key factors to affect the sub-threshold swing is the residual excess holes accumulated in source junction. From the results of poly-Si TFT with degraded buffer layer and partial metal shielding layer, the model for mechanism of increased sub-threshold swing under illumination is proposed. The electrical degradation of n-channel poly-Si TFT has been investigated under dynamic voltage stress by capacitance-voltage (C-V) measurement. In C-V measurements, the fixed charges in the gate oxide film of TFTs are not affected by the applied small signal, whereas the trap states in the band gap would respond to the applied frequency, so that the dominant degradation mechanism of poly-Si TFTs can be evaluated. Our experimental results show that the degradation of n-type TFTs is caused by additional trap states located at the drain and the source junction in the poly-Si thin film. Furthermore, through the experimental results of the C-V characteristics measured at 10 kHz and 1 MHz, we can infer that the tail states produced by the strained bounding in poly-Si film are mostly responsible for the electrical degradation of n-channel poly-Si TFTs after dynamic stress. In addition, this work also studies the electrical degradation of laterally grown poly-Si TFTs under dynamic voltage stress. The experimental results show the severity of the degradation of poly-Si TFTs with a protruding grain boundary. The concentration of the electric field in the protrusion region was verified by capacitance-voltage measurements and simulation of the device characteristics. These results reveal that more electrons are induced at the grain boundary of the poly-Si channel because of the relatively high electric field in the protrusion region. Based on these data, this study proposes a model to explain the enhanced electrical degradation of poly-Si TFTs with a protruding grain boundary, generated by laser-crystallized lateral growth technique. A new pixel design and driving method for active-matrix organic light emitting diode (AMOLED) display using poly-Si TFT is proposed. The new circuit consists of five TFTs and one capacitor to eliminate the variation in the threshold voltage of the TFTs, and the drop in the supply voltage in a single frame operation. The proposed pixel circuit has been verified to realize uniform output current by the simulation work using HSPICE software. The simulated error rate of the output current is also discussed in this paper. The novel pixel design has great potential for use in large size and high resolution AMOLED displays. Finally, this work also presents a new a-Si:H pixel circuit with source-follower type compensation method for large-size AMOLED displays. The proposed pixel circuit consists of five TFTs and one capacitor to compensate the shift in the threshold voltage of the driving TFT and OLED used in AMOLED and the compensation process is simplified by the proposed driving scheme. The high immunity to degradation of TFT and OLED in proposed pixel has been verified by the simulation work using HSPICE software. The novel pixel design has great potential for use in large-size AMOLED displays.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009224508
http://hdl.handle.net/11536/76699
Appears in Collections:Thesis


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