標題: 以二氧化鉿為基底之高介電常數閘極介電層中的電荷捕捉與逃逸之電特性分析
Electrical Characterization of Charge Trapping and De-trapping in Hf-Based High-k Gate Dielectrics
作者: 吳偉豪
Wei-Hao Wu
陳茂傑
崔秉鉞
Mao-Chieh Chen
Bing-Yue Tsui
電子研究所
關鍵字: 電特性分析;電荷捕捉;電荷逃逸;高介電常數介電層;electrical characterization;charge trapping;charge de-trapping;high-k dielectric
公開日期: 2006
摘要: 本論文主要探討的是,以二氧化鉿為基底之高介電常數閘極介電層中的電荷捕捉與逃逸之各種不同的電特性分析。與傳統的二氧化矽(SiO2)或氮氧化矽(SiON)閘極氧化層不同的是,以二氧化鉿為基底之高介電常數閘極介電層具有相當嚴重的可靠度問題—臨界電壓的不穩定性,起因於早已存在的主體缺陷中的快速與緩慢的電荷捕捉與逃逸現象,特別是對於處在矽基底電子注射狀態下的N型金氧半場效電晶體而言。我們發現,在偏壓高溫不穩定性(bias-temperature instability, BTI)應力測試的應力/量測循環之中,這些被捕捉的電荷載子將導致半導體元件中臨界電壓的偏移、汲極電流的衰減,以及通道載子移動率的變異;而且能夠被偵測到的被捕捉電荷載子數目與切換和量測的時間延遲長短有著相當密切的關係,這是因為一旦閘極應力偏壓被移開的時候,將導致快速的瞬間電荷逃逸現象發生。因此,我們必須使用適當的電特性分析方法,以瞭解在以二氧化鉿為基底的高介電常數閘極介電層中之快速與緩慢的電荷捕捉與逃逸現象的物理機制,以及這些現象對於效能評估所造成的衝擊,無論是在個別元件或整體電路的層級而言。 第一章簡介了一般性的背景知識與研究動機,並從材料與電特性等方面來說明為什麼我們要用以二氧化鉿為基底的高介電常數閘極介電層來取代傳統的二氧化矽閘極氧化層。接著說明因電荷捕捉與逃逸現象所造成的臨界電壓不穩定性,此一議題已被廣泛認定是高介電常數閘極介電層中嚴苛的可靠度問題之一,其中包含了快速與緩慢的高介電常數閘極介電層缺陷。最後,簡單說明本論文的組織架構,以提供此一學術研究之綱要概述。 第二章描述了在正偏壓高溫不穩定性(positive bias temperature instability, PBTI)應力測試下,N型金氧半場效電晶體中之鉿矽酸鹽(HfSiO)/二氧化矽(SiO2)高介電常數雙層閘極堆疊的臨界電壓不穩定性。我們廣泛探討了在正偏壓高溫不穩定性應力測試下的各項基本元件特性的劣化行為以及電荷捕捉時的載子傳輸機制,並採用一具有離散捕捉時間常數的電荷捕捉物理模型(延伸的指數成長模型)來描述並預測此一電荷捕捉行為。此外,我們也一併探討了應力測試電壓、溫度,以及閘極堆疊結構對於電荷捕捉行為的相關性,以瞭解在鉿矽酸鹽/二氧化矽高介電常數雙層閘極堆疊中之電荷捕捉的物理特性。第三章描述了處在靜態與動態正偏壓應力測試下,二氧化鉿(HfO2)/二氧化矽(SiO2)高介電常數雙層閘極堆疊中的電荷捕捉與逃逸行為。我們發現,如果反向的復甦偏壓強到足以將之前捕捉的電荷載子清除乾淨的話,相似的電荷捕捉與逃逸行為將不斷地重覆出現在連續施加的靜態應力/復甦循環之中。根據這些發現,我們可以推論,這些高介電常數介電層缺陷應是早已存在於二氧化鉿高介電常數介電層中的主體缺陷,而且在這些應力測試循環之中應該沒有新的高介電常數介電層缺陷產生。接著,我們驗證了,假使逃逸的電荷載子數目遠小於注入的總電荷載子數目,靜態與動態的正偏壓應力測試將呈現相似的電荷捕捉基本特性。此外,我們可以藉由改變在特定頻率下之應力脈衝波形的責任週期大小,來觀察及分析動態正偏壓應力測試下的瞬間充電行為,並證實一以有效應力時間為參數的通用電荷捕捉模型。 第四章說明了一採用五元素電路模型的雙頻電容—電壓校正方法,此方法可廣泛應用於高介電常數閘極介電層與超薄氧化層。此一通用的五元素電路模型同時考量了靜態與動態的介電層能量損耗,以及半導體電容常有的寄生元件,譬如來自於基底/井區的串聯電阻與來自於傳輸線/量測系統的串聯電感。再者,這一個五元素電路模型可依據閘極漏電流之大小,轉變為其他兩種不同的四元素電路模型,以簡化其計算與分析。我們發現,使用此一雙頻電容—電壓校正方法,可有效修正低漏電之高介電常數閘極介電層中的箝制與擴大電容—電壓圖形,並可解釋各寄生元件的面積效應及其物理起源。此外,此一雙頻電容—電壓校正方法亦可有效抑制超薄氧化層中因量子穿隧漏電流而引起的嚴重電容值墜落現象,並可另外搭配適當的電容—電壓模擬軟體(已考慮多晶矽空乏效應與量子效應),以求取超薄氧化層的等效氧化層厚度。第五章闡釋了如何使用低頻電容—電壓量測方法,來決定在二氧化鉿/二氧化矽高介電常數雙層閘極堆疊中的邊界缺陷之空間與能階分佈。邊界缺陷,在此代表的是那些能夠被偵測到的快速高介電常數介電層缺陷,一般都座落在高介電常數介電層/二氧化矽氧化層的介面附近,而這些邊界缺陷能夠和底部的矽基板經由量子直接穿隧效應作即時的電荷載子交換。我們發現,假使這些邊界缺陷的瞬間充電與放電行為能夠跟得上電容量測的小訊號頻率,則在低頻所量測到之增加的電容值大小,可視為一與理想介電層電容值並聯的邊界缺陷電容值。如同物理模型所預測的,此一邊界缺陷電容值已被證實與待測元件的閘極面積成線性相關,而且此一邊界缺陷電容值的大小也與鉿矽酸鹽薄膜中的矽成分高低有著相當密切的關係。此外,此一邊界缺陷電容值與量測頻率和閘極偏壓之間的關係式,也可經由適當的轉換,成為自矽基底表面的穿隧距離和自二氧化鉿導帶邊緣的缺陷能階深度。以一穿透梯形位能障礙的彈性直接穿隧物理模型為理論基礎,我們能夠藉由一平滑的三維網線,來描述在二氧化鉿/二氧化矽高介電常數雙層閘極堆疊中的邊界缺陷之空間與能階分佈。此外,根據這些物理模型萃取的結果,我們可以推論絕大部分、早已存在的高介電常數介電層缺陷均分佈在二氧化鉿的主體介電層之中,而且有相當可觀的部分是座落在低能階之位置。 第六章闡明了如何使用低頻電荷泵浦(charge pumping)方法,來分析在二氧化鉿/二氧化矽高介電常數雙層閘極堆疊中的邊界缺陷之瞬間充電與放電行為。如同在低頻電容—電壓圖形中的邊界缺陷電容值一般,在低頻電荷泵浦方法中所量測到的額外每單位循環再結合電荷載子數目,皆可歸因於反覆的多數與少數載子再結合,而此一現象主要發生於高介電常數介電層/二氧化矽氧化層介面附近的邊界缺陷。藉由改變輸入脈衝波形的上升/下降時間、峰值與基值水平電壓,以及責任週期,我們可以對邊界缺陷之瞬間充電與放電行為的穿隧路徑及物理機制有更深入的瞭解,我們並發現瞬間充電與放電現象可能發生在僅僅50至100奈秒之間。以一具有對稱的前向與反向穿隧時間常數之彈性直接穿隧物理模型為理論基礎,我們同樣能夠得到邊界缺陷的空間與能階分佈,並以一平滑的三維網線來作描述。同時,我們比較了低頻電容—電壓量測與低頻電荷泵浦這兩種適用於邊界缺陷的分析方法,並對邊界缺陷的空間與能階分佈得到一致的結論。 最後,第七章總結本論文的各項發現與貢獻,並指出本論文中尚未被清楚理解或尚未有強烈證據支持的研究主題。這些延伸的研究主題能夠幫助我們指引出未來的技術發展方向,並值得投入大量的研究活動去深入探討。
This dissertation studies the charge trapping and de-trapping in Hf-based high-k gate dielectrics through various electrical characterizations. Unlike the conventional SiO2 or SiON gate oxides, Hf-based high-k gate dielectrics are known to suffer from the serious reliability concern of threshold voltage instability due to the fast and slow charge trapping and de-trapping in the pre-existing bulk traps in Hf-based high-k gate dielectrics, especially under the substrate electron injection conditions in high-k nMOSFETs. These trapped charge carriers are believed to cause the threshold voltage shift, drain current degradation, and channel mobility variation during the stress/measure cycles of bias temperature instability (BTI) stress, and the number of trapped charge carriers which can be detected depends greatly on the switching and measurement time delays due to fast transient charge de-trapping when the stress bias voltage is removed. Therefore, appropriate electrical characterization methods should be employed to understand the physical mechanisms of fast and slow charge trapping and de-trapping in Hf-based high-k gate dielectrics and their impacts on the performance evaluation whether in the device or circuit level. Chapter 1 introduces the general background and motivations about why should we use the Hf-based high-k gate dielectrics to replace the conventional SiO2 gate oxides in terms of the electrical and material properties. The threshold voltage instability induced by charge trapping and de-trapping has been identified as one of the most critical reliability issues in Hf-based high-k gate dielectrics, including the charge trapping and de-trapping in fast and slow high-k traps. Moreover, the organization of this dissertation will be briefly described and explained to give the outline of this academic study. Chapter 2 describes the threshold voltage instability in nMOSFETs with dual- layer HfSiO/ SiO2 high-k gate stack under static positive bias temperature instability (PBTI) stress. The fundamental characteristics and carrier transport mechanism of charge trapping under static PBTI stress are investigated extensively, and a physical model of charge trapping with dispersive capture time constants (stretched exponential growth model) has been employed to describe and to predict the charge trapping behavior. In addition, the dependences of stress voltage, temperature, and gate stack structure are studied to further understand the physical nature of charge trapping process in the dual-layer HfSiO/SiO2 high-k gate stack. Chapter 3 depicts the charge trapping and de-trapping behaviors in the dual-layer HfO2/SiO2 high-k gate stack under static and dynamic positive bias stress. Similar charge trapping and de-trapping behaviors could be observed and repeated during the consecutive static stress/recovery cycles if the recovery bias voltage is strong enough to clean up the previously trapped charge carriers. Based on these findings, we may conclude that these high-k traps are the pre-existing bulk traps in the HfO2 high-k dielectric and that no additional high-k traps are generated during the stress cycles. Then the fundamental characteristics of charge trapping under dynamic positive bias stress has been demonstrated to be identical with those under static positive bias stress if the de-trapped charge carriers could be neglected as compared to the total injected charge carriers. The transient charging behavior under dynamic positive bias stress could be observed and analyzed by varying the duty cycles of stress pulse waveform at a specific frequency, and a universal charge trapping model has been proved in terms of the effective stress time. Chapter 4 explains the two-frequency capacitance-voltage (C-V) correction method using a five-element circuit model for high-k gate dielectrics and ultrathin oxides. This general circuit model of five elements considers both the static and dynamic dielectric energy losses and parasitic components such as the substrate/well resistance and cable/system inductance, and this five-element circuit model could be modified as another two four-element circuit models to simply the calculations, depending on the gate leakage current. The clamped and amplified C-V curves of low-leakage high-k gate dielectrics could be effectively eliminated by using this two-frequency C-V correction method, and the area dependence and physical origin of parasitic components have also been clarified in detail. Also, the severe capacitance drop in the C-V curves of ultrathin oxides could be effectively suppressed and then simulated to obtain the equivalent oxide thickness (EOT) of ultrathin oxides by using the C-V simulation program which has already taken the poly depletion and quantum size effects into account. Chapter 5 illustrates the space and energy distribution of border traps in the dual-layer HfO2/SiO2 high-k gate stack by the low-frequency capacitance-voltage (C-V) measurements. Border traps here represent the detected fast high-k traps located near the high-k/oxide interface which can instantly exchange the charge carriers with the underlying Si substrate through direct tunneling. The capacitance increase at low frequencies could be regarded as the border trap capacitance which is in parallel with the ideal dielectric capacitance if the transient charging and discharging of these border traps could follow the small-signal measurement frequency immediately. Border trap capacitance has been proved to be linearly proportional to the gate area as expected and highly associated with the Si composition in HfSiO films, and its frequency and gate bias voltage dependences could also be transformed into the relationships of the tunneling distance from Si substrate surface and the trap energy depth from HfO2 conduction band edge. Based on a physical model of elastic direct tunneling through trapezoidal potential barriers, the space and energy distribution of border traps in the dual-layer HfO2/SiO2 high-k gate stack could be smoothly profiled as a 3D-mesh. According to the model-extracted results, we may conclude that most of the pre-existing high-k traps are located in the HfO2 bulk layer and that considerable parts of these traps are positioned at the shallow energy levels. Chapter 6 clarifies the transient charging and discharging of border traps in the dual-layer HfO2/SiO2 high-k gate stack by low-frequency charge pumping method. Similar to the border trap capacitance at low-frequency C-V curves, additional recombined charge per cycle at low-frequency charge pumping measurements could be attributed to the repetitive recombination of majority and minority carriers which instantly tunnel into and out of the border traps located near the high-k/oxide interface. The tunneling path and physical mechanism of transient charging and discharging behaviors of these border traps could be further understood by varying the rise time and fall time, peak and base level voltages, and duty cycles of input pulse waveform, and the transient charging and discharging behaviors may occur within only 50-100 ns. Based on an elastic direct tunneling model with symmetric forward and reverse tunneling time constants, the space and energy distribution of border traps could also be obtained as a smoothed 3D-mesh. A comparison of analysis results was made between the low-frequency C-V measurement and low-frequency charge pumping method, and identical conclusions were drawn from these two different methods. Finally, chapter 7 summarizes the findings and contributions of this dissertation, and also indicates the topics that have not yet been understood clearly nor verified with strong evidence supports. These topics could help us direct the development of future technologies and deserve to be studied with great activities.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008911502
http://hdl.handle.net/11536/76657
Appears in Collections:Thesis


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