標題: 32-BIT RISC CPU實作-使用ASIP方式
32-Bit RISC CPU implementation – Using ASIP approach
作者: 謝宜軒
i-hsuan hsieh
陳昌居
chang-jiu chen
資訊學院資訊學程
關鍵字: 微處理機;CPU;Processor;ASIP;RISC
公開日期: 2005
摘要: 本論文研製之ASIP(Application Specific Instruction Set Processor)於目前的SOC中使用的相當廣泛,一個SOC中有時使用一個以上的ASIP。而ASIP與一般的general purpose Processor最大的不同,在於ASIP執行的程式一般都是固定於chip上,而非於DRAM, SRAM上的不同程式。所以為了達到CHIP area與Performance的需求,ASIP 的generation tool 都可以方便使用者自行定義instruction set, 內部的pipe line stage, function unit、、等。在定義好之後,可以自動產生HDL source及compiler, simulator等tool set, 使的user可以針對某個特殊應用來設計所需的ASIP使用。 我們經過評估後決定使用日本Osaka University 的ASIP Meister tool(http://www.eda-meister.org/), Tool這套可以產生VHDL RTL code 及C compiler generator files for COSY compiler generator (http://www.ace.nl)。ASIP在定義指令集及架構採用graphic GUI, 並且tool可以在RTL code合成前就能預估出gate count, power, speed供參考。我們預備以32-bit RISC架構來設計一個ASIP, 並實做出一個晶片。對ASIP的設計流程作一完整實作及瞭解,並驗證ASIP meister Tool功能。對於在SOC設計例如網路、圖形、數位電視、、等應用需要ASIP時,可供參考。 設計的CPU為32 bit RISC, 5 stage pipe line, instruction set 以OPEN source的OPEN RISC (http://www.opencores.org/projects.cgi/web/or1k)為架構。因為我們無法取得COSY compiler generator, 因此必須使用OPEN RISC的GNU tool chain的C compiler.因為無COSY conmpiler generator, 使我們在instruction set的調整受限,但是可以評估以ASIP方式的CPU實作結果。 在得到ASIP 產生的RTL code之後, 我們再以Synopsys等CIC(www.cic.org.tw)提供的工具以UMC .18的cell lib, 依據CIC的要求,進行 Scan chain insert, IC layout APR(Auto Place and Route), DRC/LVS 等完整IC 下線的工作。
ASIP(Application Instruction Set Processor) are commonly used in today’s SOC design. Some SOC chips use more then one ASIPs. The most difference between ASIP and a general purpose CPU is that ASIP usually execute instructions fixed in chip instead of different programs in RAM. To optimize the chip area and performance, ASIP tool can let user generate own instruction set, pipe line state, function unit. And generate RTL code, compiler, simulator of the dedicated ASIP to be used. We select the ASIP meister tool (http://www.eda-meister.org/) from Osaka University as our ASIP design tool. Which can generate VHDL source code and C compiler generator files for COSY compiler generator (http://www.ace.nl) . The ASIP meister use graphic interface in defining instructions and pipe line stages. And can estimate the gate count, power, performance before chip implementation. We will define a 32-bit RISC CPU, and generate RTL code and implement real chip. For verify ASIP design flow and the ASIP meister tool. For SOC design such as network, graphic, digital, … applications that need ASIPs, the ASIP methodology can be used. Our ASIP is a 5 stage 32bit RISC, and the instruction set is from open source OR1K (http://www.opencores.org/projects.cgi/web/or1k). Since we could not get the COSY compiler generator, we have to use the OR1K GNU C compiler. So we are not able to refine instructions, but we still can evaluate the ASIP approach for a CPU design. After the RTL code, we will prepare the chip implementation. We will use UMC .18 um cell lib to synthesis by Synopsis, and other tools from CIC to do scan chain insert, APR(Auto Place and Route), DRC/LVS for chip tape out requirement by CIC.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008867590
http://hdl.handle.net/11536/76635
Appears in Collections:Thesis


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