標題: Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap
作者: Wei, Lan
Deng, Jie
Chang, Li-Wen
Kim, Keunwoo
Chuang, Ching-Te
Wong, H. -S. Philip
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: CMOS;contacted gate pitch;device geometry;device scaling;footprint;parasitic
公開日期: 1-二月-2009
摘要: We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.
URI: http://dx.doi.org/10.1109/TED.2008.2010573
http://hdl.handle.net/11536/7663
ISSN: 0018-9383
DOI: 10.1109/TED.2008.2010573
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 56
Issue: 2
起始頁: 312
結束頁: 320
顯示於類別:期刊論文


文件中的檔案:

  1. 000262816800022.pdf