Variation-Tolerant Nanoscale CMOS SRAM Design
|關鍵字:||抗變異;次臨界;記憶體;靜態隨機存取;低功率;積體電路設計;variation-tolerant;subthreshold;memory;static random access;low power;VLSI|
Since low-power embedded memory with low minimum operating voltage (VMIN) is desired to reduce overall system power dissipation for portable and handheld devices and for ultra-low power bio-medical and wireless sensor applications, and it is crucial to minimize energy per operation to extend battery life. The minimum energy operation is reported to operate the circuits in subthreshold region, slightly below the threshold voltage. First, for sub-threshold VLSI, we present an energy efficient bootstrapped CMOS driver to enhance switching speed for driving large RC load for ultra-low-voltage CMOS VLSI. The proposed bootstrapped driver eliminates the leakage paths in the conventional bootstrapped driver to achieve and maintain more positive and negative boosted voltage levels of the boosted nodes, thus improving boosting efficiency and enhancing driver switching speed. Measured performance from test chips implemented with UMC 65nm low-power CMOS technology (VTN≈VTP≈0.5V) indicates that the proposed driver provides rising-delay improvement of 37%-50% and falling-delay improvement of 25%-47% at 0.3V for loading ranging from 0 to 24mm long M6 metal line compared with the conventional bootstrapped driver. Although designed and optimized for subthreshold ultra low-voltage operation, the proposed bootstrapped driver is shown to be advantageous at higher nearly-threshold supply voltage as well. The proposed driver provides rising delay improvement of 20% to 52% and falling delay improvement of 23%-43% for VDD ranging from 0.3V to 0.5V while consuming about 15% less average power than the conventional bootstrapped driver driving 16mm long M6 wire. Then, we present an ultra-low power 72Kb 9T Static Random Access Memory (SRAM) with a Ripple Bit-Line structure and Ripple-initiated Negative Bit-Line Write-assist. The Ripple Bit-Line scheme provides over 40% Read access performance improvement for VDD below 0.4 V compared with the conventional Hierarchical Bit-Line (HBL) structure. A variation-tolerant ripple-initiated NBL Write-assist scheme with the transient negative pulse coupled only into the single selected Local Bit-Line segment is employed to enhance the NBL boosting efficiency and reduce power consumption. The 72Kb SRAM test chip has been fabricated in UMC 40nm Low Power CMOS technology. Error free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 KHz) at 1.1 V (0.33 V) and 25 oC. The measured total power consumption is 3.94 μW at 0.33 V, 500 KHz and 25 oC. And follow up the previous design; we present a two-port disturb-free 9T subthreshold SRAM cell with independent single-ended Read and Write Bit-Lines and cross-point data-aware Write structure. The cell provides robust variation tolerance for subthreshold application and facilitates bit-interleaving architecture for enhanced soft error immunity. This design employs a variation-tolerant Line-Up Write-Assist scheme where the timing of area/energy-efficient boosted Write Word-Line and negative WBL are aligned and triggered/initiated by the same low-going Global WBL to maximize the Write-ability enhancement. A 72kb SRAM test chip is implemented in UMC 40nm Low-PowerCMOS technology. 65 dies are characterized with full memory complier product qualification patterns. Full functionality is achieved for VDD ranging from 1.5V to 0.32V without any redundancy. The measured maximum operation frequency is 260MHz (450kHz) at 1.1V (0.32V) and 25oC. At 0.325V and 25oC, the chip operates at 600kHz with 5.78μW total power and 4.69μW leakage power, offering 2X frequency improvement compared with 300kHz of our previous 72kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (Power/Freq/IO) at 0.325V and 25oC is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design. We also present a novel subthreshold 9T SRAM cell with row-based Word-Line and column-based data-aware Write Word-Lines. The decoupled Read port and cross-point Write structure provide a disturb-free cell and facilitate bit-interleaving architecture. Compared with a previous cross-point Write 9T subthreshold SRAM cell reported in the literature, the proposed 9T SRAM cell offers comparable stability with improved Read performance and variation-tolerance. Monte Carlo simulations based on UMC 40nm Low-Power technology indicate that the BL access time improves by 15.35% to 17.37%, and the variation (σ of BL access time) improves by 5.12% to 9.22% for VDD ranging from 0.3V to 0.6V. Based on a 72Kb SRAM macro design in UMC 40LP process, the proposed 9T cell achieves about 9% better chip access time at SS corner for VDD ranging from 0.3V to 0.45V. In addition to subthreshold design, we presents a 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip tracking and negative source-line write-assists. The TPG facilitates lower NAP mode voltage/power and faster wake-up for the cell array, while low-swing GRBL reduces the dynamic read power. A variation-tolerant charge-sharing write scheme, where the floating “Low” global write bit-line (GWBL) is used to capacitively couple down the local bit-line, is combined with a cell Vtrip-tracking and NVSL write-assists to improve the write-ability. The 256kb test chip is implemented in UMC 40nm low-power CMOS technology. Error-free full-functionality is achieved from 1.18GHz at 1.5V to 100MHz at 0.65V without redundancy. The TPG scheme reduces the power by 70% (55%) at 1.5V (0.5V) in NAP mode. The low-swing GRBL reduces dynamic read power by 3.5% (8%) at 1.1V (0.65V). The VTP-WA and NVSL-WA improve the write VMIN by 50mV (from 0.7V to 0.65V) and reduce write bit failure rate by 2.75x at 0.65V. Due to limited resources and time, plenty to-be-published and ongoing future works, including several single-port, dual-port SRAM designs from 40nm to 28nm, and further subthreshold SRAM designs even ultra-low voltage 2-port register file are mentioned in brief.