標題: 穿隧式場效電晶體與鰭式場效電晶體的隨機變異特性於元件及邏輯電路之研究與分析Investigation and Analysis of Random Variations on TFET and FinFET Devices and Logic Circuits 作者: 陳倩如Chen, Chien-Ju莊景德Chuang, Ching-Te電子工程學系 電子研究所 關鍵字: 穿隧式場效電晶體;鰭式場效電晶體;功函數變異;線邊緣粗糙程度;Verilog-A;TFET;FinFET;Work Function Variation;Line-Edge Roughness;Verilog-A 公開日期: 2014 摘要: 本論文使用三維TCAD (Technology Computer Aided Design)蒙地卡羅 (Monte Carlo) 混合模式模擬器進行模擬，研究隨機變異特性對同質接面穿隧式場效電晶體與鰭式場效電晶體元件的影響。並進一步利用HSPICE (Simulation Program with Integrated Circuit Emphasis)查表式Verilog-A模型模擬考慮元件變異性的邏輯電路操作在次臨界區的表現。完整的比較與分析分成下面兩個部分。 第一個部分，我們比較功函數變異與線邊緣粗糙程度對於穿隧式場效電晶體與鰭式場效電晶體元件臨界電壓、次臨界斜率、開電流、關電流及閘極電容等方面的影響。模擬結果顯示：隨機變異特性對於穿隧式場效電晶體與鰭式場效電晶體的影響會因為他們操作機制的不同而有差異。在功函數變異的影響下，此現象特別明顯。功函數變異會對鰭式場效電晶體的開電流與關電流有著相同程度的變異性；對穿隧式場效電晶體的開電流變異性很小，但關電流的變異性則相當大，而且功函數變異的格局會使其關電流有偏大的情況。而線邊緣粗糙程度對此兩種電晶體造成的閘極電容變異性比功函數變異劇烈。 第二個部分，我們模擬兩種受到隨機變異特性的電晶體使用在前瞻式進位加法器的表現變異性。模擬的結果可以與前一個部分模擬的元件開電流、關電流與閘極電容變異性做對應。隨著操作電壓的降低(約0.3伏特以下)，穿隧式場效電晶體在電路延遲與功耗延遲乘積比都有比鰭式場效電晶體較好的表現，在受到隨機變異特性的情況下也是如此。但由於穿隧式場效電晶體漏電流偏大的變異性，其漏功率變異性比鰭式場效電晶體嚴重。This thesis investigates and analyses the variability of metal-gate work function variation (WFV) and fin line-edge-roughness (fin LER) on the homojunction TFET and FinFET devices and logic circuits operating in near-threshold region by using 3D atomistic Technology Computer Aided Design (TCAD) mixed-mode Monte-Carlo simulation and look-up table based Verilog-A model HSPICE simulation. It contains two topics and is organized as follows. In the first part, we compare the impacts on TFET and FinFET device Vt, S.S.ave, Ion, Ioff and Cg,ave considering WFV and fin LER. Simulation results show that the variation sources have different impacts on TFET and FinFET devices due to the different mechanism between them. This is apparent for the cases considering WFV, that the variability of Ion and Ioff are comparable with the almost equal S.S. for FinFET, in contrast, the variability of Ion is smaller while that of Ioff is more significant for TFET due to their different dependence on the WFV patterns. In addition, the band diagram dispersion caused by WFV leads to larger Ioff distribution. The Cg,ave variation of both TFET and FinFET considering fin LER is worse than that with WFV. In the second part, we present a comparative analysis for TFET and FinFET on carry-look-ahead adder delay, PDP and leakage power considering WFV and fin LER. The simulation results are related to the variability of Ion, Ioff and Cg,ave in the first part. As the operating voltage is reducing (under ~0.3V), the delay and PDP of TFET are much better than FinFET even with the impact of random variation. However, the leakage power variability of TFET is worse than FinFET due to the worse Ioff variability and the larger Ioff trend of TFET devices. URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070150115http://hdl.handle.net/11536/76286 顯示於類別： 畢業論文