標題: A Quasi-Delay-Insensitive Microprocessor Core Implementation for Microcontrollers
作者: Chen, Chang-Jiu
Cheng, Wei-Min
Tsai, Hung-Yue
Wu, Jen-Chieh
資訊工程學系
Department of Computer Science
關鍵字: asynchronous circuit;microcontroller;micropipeline;dual-rail;Muller pipeline;quasi-delay-insensitive
公開日期: 1-Mar-2009
摘要: Microcontrollers are widely used on simple systems; thus, how to keep them operating with high robustness and low power consumption are the two most important issues It is widely known that asynchronous circuit is the best solution to address these two issues at the same time. However, it's not very easy to realize asynchronous circuit and certainly very hard to model processors with asynchronous pipeline. That's why most processors are implemented with synchronous circuit. There are several ways to model asynchronous pipeline. The most famous of all is the micropipeline; in addition, most micropipeline based asynchronous systems are implemented with single-rail bundled-delay model. However, we implemented our 8-bit microprocessor core for asynchronous microcontrollers with an alternative - the Muller pipeline. We implemented our microprocessor core with dual-rail quasi-delay-insensitive model with Verilog gate-level design. The instruction set for the target microprocessor core is compatible with PIC 18. The correctness was verified with ModelSim software, and the gate-level design was synthesized into Altera Cyclone FPGA. In fact, the model we used in this paper can be applied to implement other simple microprocessor core without much difficulty.
URI: http://hdl.handle.net/11536/7604
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 25
Issue: 2
起始頁: 543
結束頁: 557
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