標題: Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end
作者: Wu, Chung-Yu
Wang, Wen-Chieh
Shahroury, Fadi R.
Huang, Zue-Der
Zhan, Hao-Jie
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 24-GHz;CMOS;Current-mode;Receiver front-end
公開日期: 1-Mar-2009
摘要: A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-mu m 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P-(1) (dB)) of -13.5 dBm and the input-referred third-order intercept point (P (IIP3)) of -1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 x 0.72 mm(2) including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.
URI: http://dx.doi.org/10.1007/s10470-007-9130-0
http://hdl.handle.net/11536/7592
ISSN: 0925-1030
DOI: 10.1007/s10470-007-9130-0
期刊: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume: 58
Issue: 3
起始頁: 183
結束頁: 195
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