標題: 適用於奈米結構之Adaptive Kicking演算法之研究Drastic Speed up of Simulation of Nanostructure with Floating Island by Adaptive Kicking Algorithm 作者: 李哲安Lee, Zhe-An渡邊浩志Hiroshi Watanabe電信工程研究所 關鍵字: 泊松方程式;奈米結構;單電子現象;浮動區域;Poisson's equation;Floating Island;Computation;Nanostructure;Single Electron 公開日期: 2014 摘要: 浮動區域的結構在解泊松方程式時與電極互相獨立，而電極決定了解泊松方程式所需的Dirichlet邊界條件。若沒有定義邊界條件，運算時間將會大幅增加且使得3D元件模擬更加困難。為了降低運算時間，浮動閘的SPICE模擬中引入了電容的概念當作擬合參數 [1],[2]. 但必須要注意的是，當浮動區域的直徑小於德布羅伊波長時(~10nm)，表面電荷將會難以定義。然而，庫倫阻斷效應卻是以電容來進行描述[3]。為了避免在浮動區域結構中電容的模糊定義，我們在先前的研究中提出了適用於浮動區域結構的Kicking演算法[4]。 先前提出的Kicking演算法可以成功的算出浮動區域的電位而不使用任何的擬合參數。精確度可以達到計算出單顆電子的運動[4]-[6]。在此之後我們將此演算法應用於NVM可靠度之研究[6]。因為local trap與電極獨立，我們可以看做是有兩個floating island的元件結構。(i.e.; floating gate和local trap)。所需注意的是，每一個floating island都需要非常大的計算量。然而先前所提出的Kicking Algorithm 允許我們在一般的3D元件結構中同時模擬兩個浮動區域之行為[6]。若我們可以繼續縮短運算時間，將可以增加浮動區域數目並進行更多相關研究，如3D NAND flash中的charge-trapping layer。因此在本篇研究中提出了Adaptive Kicking Algorithm以大幅的縮減模擬時間，且可以避免因Kicking Step不當選擇而導致無法收斂的問題。Floating island is spatially and electrically disconnected from any electrode which can define the Dirichlet boundary condition for solving Poisson’s equation. Without the boundary condition at floating island, the computational speed is substantially decreased; and then causing 3D device simulation of nanostructures hard. To shorten the computational time, the capacitance of floating islands has been used as fitting parameter in SPICE modeling [1], [2]. Note that the surface charge is ill-defined on the surface of very small floating island whose diameter is less than de Broglie length (~10nm). Nevertheless, the coulomb blockade is described by using the capacitance [3]. To avoid the ambiguity of capacitance related to very small floating island (< 10nm), we have developed the Kicking Algorithm [4], and hence successfully have obtained the self-potential of floating island without fitting parameter with regardless of the size of floating island. The precision is equivalent to the movement of sole electron in our previous work [4]-[6]. Subsequently, we have applied this algorithm to the reliability study of real-life NVM cell transistor with a floating gate and local trap [6] and to high-K materials [7]. Since the local trap is spatially independent from any electrode, we can regard this structure as having two floating islands (i.e.; floating gate and local trap). Note here that typical diameter of local trap is about 2-3Å[6]; which is much smaller than that of quantum dot (about 3-5nm) and that floating gate is much larger (about 20-30nm). Note also that each floating island gets a high load on computation. Nevertheless, the previous Kicking Algorithm enables for 3D general-purpose device simulation with two floating islands (floating gate and local trap) with regardless of those diameters (from a few angstroms to a few deca-nanometers) [6]. If we can shorten the execution time for solving self-potential of each floating island, then we can increase the number of floating islands that we can deal with in device simulation. It may be helpful to simulate charge-trapping layer used in 3D NAND Flash; which layer is composed of many traps in thin layer. We should therefore develop new Kicking Algorithm to shorten the execution time for solving self-potential of each floating island with the precision that is equivalent to the movement of sole electron via floating island. In this work, we will propose a new Kicking Algorithm; which substantially reduces a load on computation with a floating island in nanostructure. URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070160317http://hdl.handle.net/11536/75864 顯示於類別： 畢業論文