標題: Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
作者: Wang, Chang-Tzu
Ker, Ming-Dou
電機學院
College of Electrical and Computer Engineering
關鍵字: Electrostatic discharge (ESD);gate leakage;power-rail ESD clamp circuit;silicon controlled rectifier (SCR)
公開日期: 1-Mar-2009
摘要: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mu m x 21 mu m.
URI: http://dx.doi.org/10.1109/JSSC.2008.2012372
http://hdl.handle.net/11536/7533
ISSN: 0018-9200
DOI: 10.1109/JSSC.2008.2012372
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 44
Issue: 3
起始頁: 956
結束頁: 964
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