標題: Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
作者: Ker, Ming-Dou
Wang, Chang-Tzu
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electrostatic discharge (ESD);low-voltage CMOS;mixed-voltage I/O;substrate-triggered technique
公開日期: 1-三月-2009
摘要: Two new electrostatic discharge (ESD) protection design by using only 1 x VDD low-voltage devices for mixed-voltage I/O buffer with 3 x VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 0.13-mu m 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers.
URI: http://dx.doi.org/10.1109/TDMR.2008.2008639
http://hdl.handle.net/11536/7513
ISSN: 1530-4388
DOI: 10.1109/TDMR.2008.2008639
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 9
Issue: 1
起始頁: 49
結束頁: 58
顯示於類別:期刊論文


文件中的檔案:

  1. 000263919100006.pdf