Title: Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
Authors: Ker, Ming-Dou
Hsiao, Yuan-Wen
電機學院
College of Electrical and Computer Engineering
Keywords: electrostatic discharge (ESD);impedance-isolation technique;LC-tank;noise figure power gain
Issue Date: 1-Mar-2009
Abstract: An impedance-isolation technique is proposed tor on-chip ESD protection design tor radio-frequency (RF) integrated circuits (ICs), Which has been successfully verified in a 0.25-mu m CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequently of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore. the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S(21)-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation techniques have been experimentally measured and compared, to those with the conventional double-diodes ESD Protection scheme. The proposed impedance-isolation technique had been demonstrated to he suitable for on-chip ESD protection design for RF ICs.
URI: http://dx.doi.org/10.1587/transele.E92.C.341
http://hdl.handle.net/11536/7510
ISSN: 0916-8524
DOI: 10.1587/transele.E92.C.341
Journal: IEICE TRANSACTIONS ON ELECTRONICS
Volume: E92C
Issue: 3
Begin Page: 341
End Page: 351
Appears in Collections:Articles