The Fabrication and Device Performances of Advanced Graphene Transistors
|關鍵字:||石墨烯;電晶體;平面閘極;雙切痕通道;graphene;transistor;In-plane gate;Dual-cut channel|
|摘要:||自2004年發現2D材料─石墨烯以來，石墨烯電晶體立即成為熱門的研究之一，由於石墨烯其本身載子遷移率極高，具有比矽更佳的導電性質，可實現極高速的傳輸之夢想，這對於下一代高速、高性能電晶體的研發來說是非常重要的。在這篇論文中，我們將利用低壓化學氣相沉積法 (LPCVD) 於銅箔上成長石墨烯薄膜，並藉由設計不同元件結構來探討石墨烯電晶體之特性。本篇論文分為三個部分，首先將介紹CVD石墨烯薄膜與石墨烯電晶體的製備方式，其次，我們將設計具有平面閘極 (In-plane Gate) 與背電極 (Bottom Gate) 雙閘極的電晶體結構，並探討之，我們發現到可以藉由改變平面閘極的電壓來控制石墨烯通道的費米能階。最後，我們將利用原子力顯微鏡的探針設計出具有單切痕及雙切痕通道的石墨烯電晶體，在此結構的設計下，強迫電流必須流經兩切痕之間，我們發現到隨著雙切痕區域的增加，最小電流所對應的閘極電壓會移至0 V，這些結果說明著不論在元件設計、調變費米能階或元件應用上皆是有趣的結構。|
Since the graphene ,two-dimensional material, was discovered in 2004, graphene transistors rapidly become a hot topic. Because of its high mobility and good conductivity, graphene can match the goals of high-speed operation, which is importance for the development of high-speed, high-performance transistors. In this thesis, we grow graphene on copper foil by using a low-pressure chemical vapor deposition system. By using difference sample structures, we will investigate the characteristic of graphene transistors. Generally, this thesis can be divided into three parts. Firstly, we will introduce the preparation of graphene films and graphene transistors. Next, we design dual-gated (in-plane and bottom gates) graphene filed-effect transistors and investigate it. We find that it is effective to tune Fermi level in graphene channels by changing the voltages of in-plane gates. Finally, we design one-cut and dual-cut graphene filed effect transistors scraped by using atomic force microscope tips. In these devices, the current is forced to squeeze into the path between the two cuts rather than flow directly through the graphene sheet. We have observed that the gate voltages under minimum current conditions shift toward zero bias as the sizes of the dual-cut regions increase. These results have demonstrated an interesting architecture for device fabrication, Fermi level tuning, and device applications.