Full metadata record
DC FieldValueLanguage
dc.contributor.authorLin, Chung-Kaien_US
dc.contributor.author潘 扶 民en_US
dc.contributor.authorPan, Fu-Mingen_US
dc.description.abstract當DRAMs隨著特徵尺寸的縮小到40及30奈米節點時,為了能符合金屬內連線的設計要求,並得到較低的電阻率需求及保有良好的填洞能力。氮化鈦(TiN)及鎢(W)仍是目前最廣泛分別應用在阻障層及插銷製程中,因為具有優異的沉積覆蓋率及良好的材料穩定性。在本論文中,我們主要討論化學氣相沉積條件對TiN及W在阻障層及插銷製程中對降低電阻率的影響。 在實驗中TiN阻障層的製作我們以多層堆疊取代單層沉積,以TiCl4及NH3做為CVD-TiN沉積的前驅物,當沉積完成後加以NH3做退火氮化處理降低阻障層的氯含量。利用多層堆疊沉積及NH3的退火處理可有效的降低TiN電阻率,而降低TiN膜電阻率是依堆疊次數而定,但當電阻率降至臨界多層堆疊次數後電阻率即飽和不再降低。除了使用多層堆疊方式,藉由最佳化NH3氣體流量處理及使用Ar、 N2、 H2氣體電漿後處理,亦可以增進薄膜品質降低膜應力及表面粗糙度。 CVD-W薄膜沉積使用了B2H6取代SiH4與WF6沉積反應,因為具有較大的界面自由能,W在多晶的TiN膜上異質成長緩慢,成核層沉積可得到較大的晶粒當在均質成長時則有利於持續長成較大的W晶粒,而較大的W晶粒具有較少的電子散射發生,因此改善了電阻率。結合CVD-W膜的製作及TiN阻障層的多層堆疊可將W插銷電阻率降低40-50%。zh_TW
dc.description.abstractTo scale-down dynamic random access memories (DRAMs) to the 40-30 nm nodes, it is desirable to have materials of better gap filling and lower resistivity for metal interconnects to meet the design criteria. Titanium nitride (TiN) and tungsten (W) are currently the mostly used barrier layer and plug, respectively, because of the excellent step coverage and good material stability. In this thesis, we discussed the influence of chemical vapor deposition (CVD) conditions of TiN and W thin film on the reduction in the electrical resistivity of the barrier layers and plugs. We used multi-layer deposition instead of single-layer deposition for the TiN barrier layer fabrication. Titanium tetrachloride (TiCl4) and ammonia (NH3) were used as the precursor for the CVD-TiN deposition. After the CVD deposition, the TiN layer was annealed in NH3 to reduce the chlorine content in the barrier layer. The electrical resistivity of the TiN layer can be significantly reduced by the multi-layer deposition and the NH3 annealing treatment. The resistivity reduction depends on the stacking number of the TiN layer, and the resistivity eventually saturates at a critical stacking number. In addition to the multi-stacking deposition, the film quality of the TiN barrier layer, including resistivity, stress and roughness, can also be improved by optimizing the NH3 gas flow rate during the CVD deposition and the plasma post treatment using Ar , N2 and H2 as the gas precursors of different gas flow rates. For the CVD-W deposition, we used B2H6 instead of SiH4, to react with WF6 during the nucleation stage so that large W grains were obtained. Because of the large interface free energy, the heterogeneous growth of W on the polycrystalline TiN layer is retarded and the homogeneous growth of W favors the growth of larger W grains. The larger W grain size results in a less electron scattering in the CVD-W film and, therefore, the resistivity is improved. Combining the CVD-W fabrication with multi-stacking TiN barrier layer, we can reduce the electrical resistivity of the W-plug by 40-50%.en_US
dc.title改善氮化鈦阻障層與鎢插塞之化學氣相沉積製程 以降低其電阻率之研究zh_TW
dc.titleElectrical Resistivity Minimization of Chemical Vapor Deposited Titanium Nitride Barrier layers and Tungsten plugs for Integrated Circuit Interconnectsen_US
Appears in Collections:Thesis