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dc.contributor.authorChen, Shin-Kaien_US
dc.contributor.authorWang, Bing-Shiunen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorLiu, Chih-Weien_US
dc.date.accessioned2014-12-08T15:09:38Z-
dc.date.available2014-12-08T15:09:38Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0920-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/7379-
dc.identifier.urihttp://dx.doi.org/10.1109/ISCAS.2007.378476en_US
dc.description.abstractFPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. We also propose a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5X faster than SystemC simulation on a 3GRz PentiumD PC.en_US
dc.language.isoen_USen_US
dc.titleRapid C to FPGA prototyping with multithreaded emulation engineen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ISCAS.2007.378476en_US
dc.identifier.journal2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11en_US
dc.citation.spage409en_US
dc.citation.epage412en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000251608400103-
Appears in Collections:Conferences Paper


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