標題: Rapid C to FPGA prototyping with multithreaded emulation engine
作者: Chen, Shin-Kai
Wang, Bing-Shiun
Lin, Tay-Jyi
Liu, Chih-Wei
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2007
摘要: FPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. We also propose a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5X faster than SystemC simulation on a 3GRz PentiumD PC.
URI: http://hdl.handle.net/11536/7379
http://dx.doi.org/10.1109/ISCAS.2007.378476
ISBN: 978-1-4244-0920-4
ISSN: 0271-4302
DOI: 10.1109/ISCAS.2007.378476
期刊: 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
起始頁: 409
結束頁: 412
Appears in Collections:Conferences Paper


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