標題: 在鍺通道金氧半場效電晶體上製造閘極介電層二氧化鋯/鍺堆疊結構之研究
Investigation of ZrO2/Ge Gate Stack Fabricated on Ge-Channel MOSFETs
作者: 李品輝
Li, Pin-Hui
簡昭欣
李義明
Chien, Chao-Hsin
Li, Yi-Ming
電信工程研究所
關鍵字: 鍺;場效電晶體;二氧化鋯;germanium;MOSFET;ZrO2
公開日期: 2013
摘要: 在這篇論文中,首先我們製造了以二氧化鋯為閘極介電層的鍺金氧半電容,再來我們使用了電性和物性分析來研究利用不同溫度的原子層化學沉積以及不同溫度的沉積後退火對鍺基板和二氧化鋯之間介面的影響。我們討論並使用電導方法(conductance method)來萃取介面缺陷電荷密度,也利用准靜態電容量測方法(quasi-static C-V)和貝格朗積分(Berglund integral)萃取出表面電位並探討能帶彎曲的有效程度。我們選擇250度的原子層化學沉積以及在600度的氮氣環境下進行一分鐘的沉積後退火做為我們製作元件的條件。 其次,我們成功的利用閘極後形成的製程(gate last process)做出了鍺金氧半場效電晶體。我們的p+/n接面以及p型金氧半場效電晶體的開關比分別為1.66×104和2.92×103,次臨界擺幅為119 mV/dec。我們的n+/p接面以及n型金氧半場效電晶體的開關比分別為1.51×105和1.73×104,次臨界擺幅為112.5 mV/dec。但是在介電層退火的過程中,我們的摻雜會向外擴散而造成有很大的源極/汲極串連阻抗。為了改善這個缺點,我們改變了製程的先後順序。 再來,我們利用閘極先形成的製程(gate first process)做出了鍺金氧半場效電晶體。們的p+/n接面以及p型金氧半場效電晶體的開關比分別為8.61×104和5.32×103,次臨界擺幅為125.8 mV/dec。我們的n+/p接面以及n型金氧半場效電晶體的開關比分別為1.66×104和3.02×103,次臨界擺幅為130.5 mV/dec。 最後,我們比較閘極後形成的鍺金氧半場效電晶體和閘極先形成的鍺金氧半場效電晶體。由於摻雜活化是閘極先形成的製程中最後一個高溫的步驟,所以源極/汲極的串連阻抗被大大的降低。
In this thesis, firstly ZrO2/Ge MOS capacitors are fabricated. ZrO2 was deposited by atomic layer deposition (ALD) with different conditions such as deposition temperatures and post deposition annealing (PDA) temperatures. We electrically and physically analyze the ZrO2/Ge MOS capacitors. Conductance method is discussed in detail and utilized to extract the density of interface state of the ZrO2/Ge MOS capacitors. Also, by using quasi-static C-V curve and Berglund integral, we can estimate the band bending efficiency from the extracted surface potential. We choose ALD at 250C and PDA at 600C in N2 ambient for one minute to be an optimized condition to fabricate the Ge MOSFETs. Secondly, we successfully fabricate the Ge MOSFETs using a gate last scheme. The on/off ratio of our p+/n junction and reaches 1.66×104 and 2.92×103, respectively and the subthreshold swing of p-MOSFET is 119 mV/dec. The on/off ratio of our n+/p junction and n-MOSFET reaches 1.51×105 and 1.73×104, respectively and the subthreshold swing of n-MOSFET is 112.5 mV/dec. Even so, we find, however, there is a large source/drain series resistance in our MOSFET due to the dopant out-diffusion during the high- dielectric annealing. In order to improve this drawback, we further change the fabrication from the gate last scheme to the gate first scheme. Thirdly, we fabricate Ge MOSFETs using a gate first scheme. The on/off ratio of our p+/n junction and p-MOSFET reaches 8.61×104 and 5.32×103, respectively and the corresponding subthreshold swing is 125.8 mV/dec. The on/off ratio of our n+/p junction and n-MOSFET is 1.66×104 and 3.02×103, respectively while the subthreshold swing is 130.5 mV/dec. Finally, comparison between the studied gate last and gate first MOSFETs is discussed in detail. The engineering findings of this study indicates that source/drain series resistance can be largely reduced due to more effective dopant activation caused by the last high temperature step in the gate first process.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070060326
http://hdl.handle.net/11536/73703
顯示於類別:畢業論文


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  1. 032601.pdf