標題: 1-V linear CMOS transconductor with-65 dB THD in nano-scale CMOS technology
作者: Lo, Tien-Yu
Hung, Chung-Chih
電信工程研究所
Institute of Communications Engineering
公開日期: 2007
摘要: This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB TTID can be achieved for a 1 MHz 700 mV(pp) differential input. Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 mu W. Simulation results demonstrate the agreement with theoretical analyses.
URI: http://hdl.handle.net/11536/7346
http://dx.doi.org/10.1109/ISCAS.2007.378787
ISBN: 978-1-4244-0920-4
ISSN: 0271-4302
DOI: 10.1109/ISCAS.2007.378787
期刊: 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
起始頁: 3792
結束頁: 3795
顯示於類別:會議論文


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  1. 000251608405035.pdf