Title: 40奈米製程技術操縱在低操縱電壓的256-Kb 8T 靜態隨機存取記憶體
40nm Low Vmin 256-Kb 8T SRAM Design
Authors: 張智皓
Chang, Zhi-Hao
Chuang, Ching-Te
電子工程學系 電子研究所
Keywords: 8T靜態隨機存取記憶體;8T SRAM
Issue Date: 2013
Abstract: 近年來,許多新的替代性記憶體元件被提出以及研究,由於靜態隨機存取記憶體具有較快的存取速度,主要被廣泛應用在高效能的處理器以及嵌入式系統中的快取記憶體。由於簡單的架構、快速的操作速度以及高容量密度的優勢,傳統的6T靜態隨機存取記憶體在近幾年被廣泛的使用。隨著環境保護概念的高漲,綠色能源議題逐漸受到重視。低功率消耗、低操作電壓的電路逐漸成為今日SoC晶片設計的趨勢。然而,傳統的6T靜態隨機存取記憶體難以在低電壓中操作,因此,數種不同適用於低電壓操作的靜態隨機存取記憶體元件被相繼提出。其中,8T靜態隨機存取記憶體被視為是一個適合的選擇,由於只需犧牲少量的額外面積以及操作速度。 本篇論文提出一個新的雙端無干擾8T靜態隨機存取記憶體架構,並搭配所提出的細胞轉換電壓追蹤協助寫入技術以及交點式寫字元線電壓提升協助寫入技術來增加8T靜態隨機存取記憶體細胞的寫入能力。為了低功率消耗電路應用,我們也提出了低電壓全域讀取位元線技術。為了提升8T靜態隨機存取記憶體的操作速度,我們也加入了漣波位元線讀取架構來增進電路的操作速度。我們將本篇中所提出的技術設計出一顆容量為256-Kb,可操作在低電壓的8T靜態隨機存取記憶體電路,並透過下線實現在聯電40奈米低功耗互補金屬半導體製程上,測試晶片測量的工作電壓範圍可以涵蓋1.1V到0.5V,在1.1V,常溫25度C下,電路工作效能最高可以達到620MHz。
In recent years, many novel alternative memory devices have been proposed and researched. Because better access speed of Static Random Access Memory (SRAM), SRAMs are widely used as cache memory in high performance processor and embedded system. Because of the advantages of simple structure, high operation speed and high capacity density, the conventional 6T SRAM is the most widely used in recent years. As environmental protection consciousness, the green power becomes an increasingly important issue in todays. Low-Power and Low-Voltage circuit design becomes a major trend in SoCs recently (System-On-Chip) in todays. However, conventional 6T SRAM is hardly used to operate in low voltage. Thus, several low voltage SRAM cells are proposed. The disturb-free 8T cell is viewed as appropriate choice for low voltage application. The 8T bit-cell occupies lightly addition area and decreases the operation speed relative to conventional 6T cell. This thesis presents a novel two-port disturb-free 8T SRAM cell with cell Vtrip tracing write assist (CVTWA) and cross-point write word line boosting to improve the write-ability. For low power application, we propose the low-swing GRBL technique. To improve performance, we also apply the ripple BL structure to enhance operation speed of test chip. The proposed 8T SRAM cell is demonstrated by a 256-Kb SRAM macro in UMC 40-nm low-power CMOS technology. Measured full functionality is error-free from 1.1V down to 0.5V. The measured maximum operation frequency is 620MHz at 1.1V and 25℃.
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