標題: Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM
作者: Shih, Che-Hua
Huang, Juinn-Dar
Jon, Jing-Yang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Design automation;generators
公開日期: 1-五月-2009
摘要: Verifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation. approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.
URI: http://dx.doi.org/10.1109/TVLSI.2008.2006042
http://hdl.handle.net/11536/7333
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2008.2006042
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 17
Issue: 5
起始頁: 723
結束頁: 727
顯示於類別:期刊論文


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  1. 000265457700012.pdf