標題: A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-Q Above-IC Inductors
作者: Wang, Wen-Chieh
Huang, Zue-Der
Carchon, Geert
Mercha, Abdelkarim
Decoutere, Stefaan
De Raedt, Walter
Wu, Chung-Yu
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: CMOS;electrostatic discharge (ESD) protection;45 nm;K -band;low-noise amplifier (LNA)
公開日期: 1-May-2009
摘要: A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input I dB compression point (IP(-1) (dB))is - 9.5 dBm and the input referred third-order intercept point (P(IIP3)) is +2.25 dBm. It is-operated with a I V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for PF ICs above 20 GHz.
URI: http://dx.doi.org/10.1109/LMWC.2009.2017611
http://hdl.handle.net/11536/7330
ISSN: 1531-1309
DOI: 10.1109/LMWC.2009.2017611
期刊: IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS
Volume: 19
Issue: 5
起始頁: 326
結束頁: 328
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