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dc.contributor.author連崇德en_US
dc.contributor.authorLien, Chong-Deen_US
dc.contributor.author崔秉鉞en_US
dc.contributor.authorTsui, Bing-Yueen_US
dc.date.accessioned2014-12-12T02:37:19Z-
dc.date.available2014-12-12T02:37:19Z-
dc.date.issued2013en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT070050106en_US
dc.identifier.urihttp://hdl.handle.net/11536/73230-
dc.description.abstract由於碳化矽具有高崩潰電場和高導熱係數,應用於高溫高壓的元件是非常好的半導體材料。對於高壓元件而言,磊晶層的品質會影響到導通電阻、崩潰電壓和逆偏漏電,所以是非常重要的一環。深層暫態能譜分析能夠測量出缺陷能階、捕獲截面積,以及缺陷密度。此外,深層暫態能譜分析對於缺陷擁有高靈敏度,而且與其它偵測系統比起來相對容易去架設,因此我們選擇深層暫態能譜分析來偵測磊晶層之中的缺陷。而碳化矽中最廣泛的高壓元件應用就是蕭基位障二極體、接面二極體和接面蕭基位障二極體。為了改進接面蕭基位障二極體的特性或是簡化製程,有許多不同的結構變化。溝槽式接面蕭基位障二極體是當中最新的結構,因此我們將會利用Sentaurus TCAD tool,對於溝槽式接面蕭基位障二極體去找出其設計概要。 深層暫態能譜分析的架設是利用安捷倫半導體儀器分析儀和有溫度控制器的探測台。利用市售之深層暫態能譜分析系統來作為我們深層暫態能譜分析之系統驗證。我們的系統與市售系統在相同位置有一樣的峰值,只是我們的半導體儀器分析儀的電容量測速度比較慢,所以我們的系統有著相對弱的訊號。 試片方面製作了鎳金屬於碳化矽上的蕭基位障二極體和電容去量測磊晶層的缺陷。對於蕭基二極體而言,深層暫態能譜分析系統沒有量測到任何的缺陷。因此利用低劑量之氮離子佈值去創造缺陷。經過離子佈值之後,有非常強烈的深層暫態能譜訊號被偵測到,但是這訊號是由不同缺陷組成的,所以無法萃取缺陷能階。我們也利用不同的方式去減少離子佈值造成的缺陷,當中最有效的是 1600 度的高溫退火,幾乎所有離子佈值造成的缺陷都可以被修復,只是高溫退火同時也會產生缺陷 Z1/2,而缺陷 Z1/2可以利用高溫退火前之碳離子佈值,或是碳化矽之氧化去消除。 在本次研究中,我們也使用深層暫態能譜分析系統去量測碳化矽電容之介面能態。而電容的介電層是利用熱氧化方式生長在碳化矽上的二氧化矽。而電容量測到的深層暫態能譜並不是介面能態,反而是被介電層缺陷所主導整個分析。若是深層暫態能譜量測到含有其他種缺陷,那麼利用深層暫態能譜萃取出之介面能態將會是不正確的。而利用離子佈值後的磊晶層所做出之電容,展現了非常差的電容對電壓曲線,但是在深層暫態能譜分析方面卻與蕭基位障接面二極體有一樣的結果。 溝槽式接面蕭基位障二極體之模擬分析已經利用不同的布局參數去找到它的設計概要。當溝槽之深度加深時,因為從側壁來的額外電流,所以有比較小的臨界電壓。轉換電壓被定義成電流導通機制由單極電流 (蕭基接面電流) 轉換成雙極電流 (介面二極體電流)的電壓。與一般接面蕭基二極體相比,溝槽式接面蕭基位障二極體有比較低的轉換電壓,且導通之後有相對低的導通電阻和比較的順向導通電流。轉換電壓會隨著蕭基接面的寬度增加而增加,但是會隨著接面二極體之寬度和溝槽深度而減少。 與一般接面蕭基位障二極體相比,由於溝槽式接面蕭基位障二極體有溝槽底部有溝槽角落和較薄的磊晶層,所以會有比較低的崩潰電壓。而對於溝槽式接面蕭基位障二極體而言,崩潰發生的原因是來自於結構上的設計,因此並不能用邊緣終端技術來提高它的崩潰電壓。溝槽式接面蕭基位障二極體比較適合應用在高電流之元件應用,然而一般接面蕭基位障二極體卻是比較適合應用在高壓操作使用。 總體而言,深層暫態能譜分析系統之架設與驗證已經完成。因為氮離子佈值所造成的不同缺陷已經被偵測到,而且這些缺陷可以藉由 1600 度的退火去除,但是同時也會產生缺陷 Z1/2。深層暫態能譜分析於碳化矽電容上量到的訊號主要是介電層缺陷所主導;若是深層暫態能譜量到有其他缺陷,那麼在轉換至介面能態時,介面能態將會被高估。在相同條件下,蕭基位障二極體與電容有一樣的深層暫態能譜。溝槽式接面蕭基位障二極體的設計概要已經被分析出來,而溝槽結構會對元件的所有特性造成影響。溝槽式接面蕭基位障二極體比較適合應用在高電流之元件應用,然而一般接面蕭基位障二極體卻是比較適合應用在高壓操作使用。zh_TW
dc.description.abstractSilicon carbide (SiC) is an ideal semiconductor material for the higher power and high temperature applications due to its wide bandgap, high critical electric field, and good thermal conductivity. For high breakdown voltage device, the quality of the n- epi-layers is very important, because it influences the on-resistance, junction leakage current, and breakdown voltage of device. Deep level transient spectroscopy (DLTS) is capable of characterizing the defect energy, defect capture cross section, and density of defect quantitatively. Besides, DLTS has high sensitivity and is relatively easier than the other defect detection systems to be setup. Hence, we choose DLTS to analysis the defects in the epi-layer. The widest applications of SiC are its power diodes like Schottky barrier diode, pn diode, and junction barrier Schottky (JBS) diode. The JBS diodes have many different variations of structure for the improvement in performance or the ease of process. The trench junction barrier Schottky (TJBS) diode is one of the latest innovations, so we are going to figure out the design guidelines of the TJBS diodes by the Sentaurus TCAD tool. The setup of DLTS system consists of a semiconductor parameter analyzer with a capacitance measurement unit and a probe station with a temperature heating controller. Our DLTS system can measure the same signal but weaker signal intensity in comparison with the commercial DLTS system due to the sampling rate limitation of the capacitance measurement unit. To measure the defects in epi-layer, Ni/SiC Schottky barrier diode and SiC MOS capacitor are fabricated. For the Schottky barrier diode, there is no defect measured by our DLTS system. In order to create defects in the epi-layers, low dose nitrogen ion implantation is introduced. After ion implantation, strong signal is measured in the DLTS, but severe overlap of signals from different defects makes it hard to extract the defect energy. Different processes are applied to eliminate the defects induced by ion implantation. The most effective one is annealing at 1600 oC.Almost all the defects induced by ion implantation are eliminated. However, high temperature annealing could generate Z1/2 defect. The interface state of the SiC MOS capacitor is also investigated by our DLTS system. The gate dielectric of MOS capacitor is thermal oxide. The DLTS of MOS capacitor is dominated by oxide trap in SiO2. The signals from oxide traps overlap the signals from interface states. If the DLTS is not only composed of interface states, the direct transformation of DLTS into interface state density would be incorrect. For MOS capacitor fabricated on the ion-implanted epi-layer, poor capacitance-voltage characteristic is exhibited, but the DLTS result is the same as that measured on the Schottky barrier diode. The design guidelines of the TJBS diode have been investigated by considering different geometric parameters. As the trench depth becomes deeper, the cut-in voltage becomes slight lower due to the extra sidewall current. We define the transition voltage as the voltage at which the current transport changes from unipolar conduction (Schottky junction dominant) to bipolar conduction (pn junction dominant). TJBS diodes have lower transition voltage, and thus lower specific on-resistance and higher forward conduction current after bipolar conduction. The transition voltage increases as wider Schottky contact width, but decreases as wider pn junction width or deeper trench depth. Because of trench corner and thinner epi-layer under the pn junction due to the trench structure, relatively low breakdown voltage is observed on TJBS diodes than JBS diodes. For TJBS diodes, the breakdown voltage depends on structural design, which can be compensated by edge termination design. In conclusion, the setup and verification of DLTS system have been accomplished. Different defects after nitrogen ion implantation has been detected in Schottky barrier diode. These defects can be annihilated by a 1600 oC annealing, but meanwhile Z1/2 defect will be generated. The DLTS of MOS capacitor are dominated by oxide trap. The Dit from DLTS would be overestimated if other traps are mixed in the signal. Under the same process condition, Schottky barrier diode has identical DLTS result to MOS capacitor. The design guidelines of TJBS diodes are proposed. The trench affects all the characteristics of device. It is suggested that TJBS diodes are suitable for the higher current application, while JBS didoes are favored for high voltage application.en_US
dc.language.isoen_USen_US
dc.subject深層暫態能譜分析zh_TW
dc.subject碳化矽zh_TW
dc.subject溝槽市接面蕭基位障二極體zh_TW
dc.subjectDLTSen_US
dc.subjectSiCen_US
dc.subjecttrench junction schottky barrier diodeen_US
dc.title以深層暫態能譜分析碳化矽缺陷之研究暨溝槽式接面蕭基位障二極體之設計分析zh_TW
dc.titleA Study on the Defect in SiC by Deep Level Transient Spectroscopy (DLTS) and Design Analysis of the SiC Trench Junction Schottky Barrier (TJBS) Diodeen_US
dc.typeThesisen_US
dc.contributor.department電子工程學系 電子研究所zh_TW
Appears in Collections:Thesis


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