Title: 基於PEG演算法之低密度同位元檢查迴旋碼設計與實作
Design and Implementation of PEG based LDPC-CCs
Authors: 吳昇展
Wu, Sheng-Jhan
Lee, Chen-Yi
電子工程學系 電子研究所
Keywords: 低密度同位元檢查迴旋碼;low-density parity-check convolutional codes;progressive edge growth;LDPC-CC;PEG
Issue Date: 2013
Abstract: 低密度同位元檢查迴旋碼(LDPC-CC)於1999年首次提出,是低密度同位元檢查碼中的迴旋碼版本。由於這種迴旋碼結構,低密度同位元檢查迴旋碼高度適用於資料串流的應用。利用結尾 (tailing)與打點(puncture) 的技巧,框架大小(frame size)以及碼率(code-rate)的調整可很單純的達成。 在這個論文中,一個創新的編碼建置演算法首先被提出,這個演算法不僅考慮錯誤更正能力,也考慮了硬體實作方面。模擬結果顯示由此演算法所建置之低密度同位元檢查迴旋碼所得的錯誤更正能力比IEEE標準規格、目前流行的拆開式(unwrapping)演算法、或是最新提出的多項式(polynomial)演算法所建造之碼在不同的碼率下都有更佳的結果。第二,我們建立一個完全可調式不需重新合成、放置與繞線之雙FPGA驗證平台來加速驗證從我們所提之演算法建出之低密度同位元檢查迴旋碼。與電腦模擬比較可達加速1000倍以上效果。從平台模擬結果了解我們的演算法的確建構可實作的低密度同位元檢查迴旋碼,而且在低錯誤率區域也有出色的表現。最後,實作一個致力於人體通道通訊(body area network)低密度同位元檢查迴旋碼低功率晶片,其中這個晶片的低密度同位元檢查迴旋碼是特定為了錯誤更正能力而設計。量測結果顯示,能量效率是19.8pJ/bit/proc比現有之低密度同位元檢查迴旋碼解碼器與迴旋碼之維特比(Viterbi)解碼器有更佳的結果,且量測於0.6v資料傳輸率100Mb/s實解碼器功率僅9.9mW,符合人體通道通訊之系統鏈路預算。 總結,一個創新之低密度同位元檢查迴旋碼建置演算法在本論文中提出,其後為驗證這些低密度同位元檢查迴旋碼之雙FPGA平台,另外是一個符合人體通道通訊之系統鏈路預算之低耗低密度同位元檢查迴旋碼晶片。所有的結果都證實我們的演算法、驗證平台以及晶片設計提供低密度同位元檢查迴旋碼突破的思維與應用在下世代通訊系統的機會。
LDPC convolutional code (LDPC-CC), first introduced in 1999, is the convolutional version of LDPC code. Due to the convolutional structure, LDPC-CC is highly suitable for data streaming applications. And the variable frame size and code-rate adjustment through tailing scheme and puncturing are easily carried out. In this thesis, a novel code construction algorithm is firstly proposed for LDPC-CC construction, in which not only the performance but also the implementation aspects are considered. The simulation results show the LDPC-CCs derived from proposed algorithm outperform the codes no matter adopted by IEEE standards, derived from state-of-the-art unwrapping construction method, or found by the newly presented the polynomial based algorithm under different code-rate. Secondly, a fully configurable dual-FPGA emulation platform is built to accelerate the performance analyses of the LDPC-CCs derived from proposed algorithm without re-synthesis, placement and routing for a specific code. The speed-up compared with PC based simulations is more than 1000x. And the emulation results collected from the platform gives additional proofs that proposed algorithm generates implementable LDPC-CCs and they have outstanding performance even at the low bit error rate region. Finally, a LDPC-CC low power chip dedicated to the body area network is implemented, in which the code is specifically designed for performance requirement. The measurement results show the energy efficiency 19.8pJ/bit/proc is better than state-of-the-art LDPC-CC and convolutional code Viterbi decoder chip designs. And the decoder power 9.9mW measured at supply voltage 0.6v and data rate 100Mb/s satisfies the body area network system link budget. In summary, a novel code construction algorithm is proposed followed by a dual-FPGA true emulation platform built to verify the derived LDPC-CCs. And a low power LDPC-CC chip satisfying both the performance of the body area network and the power budget is presented. All the results are shown to examine that our proposed algorithm, platform, and chip design provide novel approaches to LDPC-CCs for next generation applications.
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