標題: A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generation
作者: Chang, Ming-Hung
Yang, Zong-Xi
Hwang, Wei
電子與資訊研究中心
Microelectronics and Information Systems Research Center
公開日期: 2007
摘要: An ADPLL-based frequency synthesizer has been designed and implemented with TSMC 130nm technology model. The cores of it are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. A new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is presented. This frequency synthesizer can operate from 300MHz to 1GHz, and achieve frequency acquisition in fifteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120ps at 300MRz. Furthermore, the design has been ported to TSMC 100nm process as a reusable IP block verification. The total power dissipation of the ADPLL-based frequency synthesizer is 1.9mW (TSMC 100nm technology) at 1GHz with a 1.2V power supply. With such specifications, it is suitable for high speed clock generation in system-on-a-chip (SoC) applications.
URI: http://hdl.handle.net/11536/7235
http://dx.doi.org/10.1109/ISCAS.2007.378250
ISBN: 978-1-4244-0920-4
ISSN: 0271-4302
DOI: 10.1109/ISCAS.2007.378250
期刊: 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
起始頁: 1137
結束頁: 1140
Appears in Collections:Conferences Paper


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