Study on the Electrical Characteristics of the PMOSFETs with the Strained SiGe S/D and Embedded SiGe Channel for the 28 nm Node and Beyond
|摘要:||在此論文中，分別針對應變源極汲極矽鍺與嵌入式矽鍺通道等二項工程提出不同結構與技術改善以提昇28奈米P型電晶體元件特性。針對應變源極汲極矽鍺，我們探討製程參數所造成的鬆弛性矽鍺對P型電晶體元件特性之通道應力衰減與矽基材缺陷形成的影響。針對嵌入式矽鍺通道，我們提出一種新穎製程方式可製作具高載子移動率，不須矽表面覆蓋卻有著較佳的閘極氧化層完整性(Gate Oxide Integrity, GOI)，來應用於28奈米電晶體元件特性之改善。
首先，針對源極汲極的矽鍺電晶體，對於製程流程上的離子佈值與毫秒式退火造成應變矽鍺的部份鬆弛性，所造成的通道應力衰減與缺陷形成於底下矽基材內而造成大量漏電，同時也造成晶片的大量彎曲變形有礙於黃光曝光的製程之28奈米P型電晶體元件特性。低能量砷離子佈值僅造成11% 應變矽鍺的部份鬆弛性，在後續的毫秒式退火下 並不會造成缺陷形成於矽基材上而造成大量漏電，同時也不會造成晶片的大量彎曲變形。然而中能量砷離子佈值僅造成51% 應變矽鍺的部份鬆弛性，在後續的毫秒式退火下，會造成缺陷形成於矽基材上而造成100倍大量漏電，同時也造成晶片的大量彎曲變形從壓應變到拉伸應變。藉由離子佈值種類的改變由砷變成磷離子和砷離子佈值的順序變化可以得到機乎完全應變無鬆弛的矽鍺而有10% 趨動電流的改善。進一步高能量砷離子佈值造成75% 應變矽鍺的大部份鬆弛性，在後續的毫秒式退火下，又不會造成缺陷形成於矽基材上，同時也不會造成晶片的大量彎曲變。此一現象了解與探討，有助於28奈米P型電晶體元件特性的改善。
其次，針對通道工程的改善，我們提出一種新穎製程方式可製作具高載子移動率的嵌入式矽鍺通道，不須矽表面覆蓋卻有著較佳的閘極氧化層完整性(Gate Oxide Integrity, GOI)，來應用於28奈米電晶體元件特性之改善。藉由源極汲極凹槽蝕刻時，緊接著額外的氣體蝕刻將(110)晶格面移除而停在(111)晶格面，並將源極與汲極打通而形成懸空的閘極與氧化層。由於此蝕刻氣體並不會與氧化層反應，所以可以再利用矽鍺沉積得到矽鍺通道。如此的結構可以得到較佳的載子移動率約26%電導通率增益(Gm)與8% Ion_Ioff 增益特性改善。同時閘極氧化層並不會被破壞且矽鍺不會與閘極氧化層反應而形成鍺氧化層，所以可以得到與矽氧化層相同的完整性與低漏電，如此一個新穎的結構可用於28奈米電晶體以及更進階的三維電晶體元件特性之改善
In this thesis, the strained SiGe source/drain (S/D) and the epitaxial SiGe channel of the PMOSFETs with the technique improvement and novel structures have been systematically investigating to boost device performance for the 28 nm node and beyond. For the former one, the impacts of the process parameters on the relaxation of the strained-SiGe induced channel stress degradation and defect formation in the under-layered Si substrate are discussed. For the later one, a novel technique to create the suspending stacked gate and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and under-layered Si substrate has been proposed for the first time to enhance the drive current gain of the 28 nm PMOSFETs. At first, for the source/drain engineering of the epitaxial strained SiGe, the degree of strained-SiGe relaxation caused by implantation significantly affected the channel stress and the formation of defects in the underlying Si substrate as well as wafer bending when the millisecond anneal (MSA) was applied to the S/D strained-SiGe in 28nm PMOSFET devices for resistance reduction. Proper implantation species selection from Arsenic (As) to Phosphorus (P) was chosen to provide a relaxation-less strained-SiGe and enhanced the channel stress. It could achieve a 10% higher current gain. The defect-free underlying Si in the millisecond-annealed 28 nm PMOSFETs devices exhibits a decrease in the junction leakage current by four orders of magnitude. A new approach to modify the implantation conditions was also developed to achieve a relaxation-less strained-SiGe layer and defect-free underlying Si substrate for the 28nm PMOSFETs. For the process parameter effects on the strained-SiGe relaxation, the formation of the induced defects in the underlying Si substrate associated with the interaction of the partly relaxed strained-SiGe layer and subsequent millisecond annealing (MSA) has been explored. Three kinds of methods including the post-SiGe implant, post-SiGe soak anneal and in-situ Ge at.% effect that were used to boost the device performance were investigated how to avoid the strained-SiGe relaxation and defect formation in the underlying Si during the MSA. All of them revealed the same phenomena that the medium relaxation of the strained SiGe either by the post-implant, post-soak anneal, or Ge content would cause significant wafer bending during the MSA. A well-controlled post-implant, post-thermal budget and Ge content must be considered to avoid wafer bending and defect formation for the advanced PMOSFETs. A design rule of the strained SiGe S/D with different active area sizes to form the defects in the underlying Si substrate during the MSA has been also proposed for the 28nm PMOSFETs. As the ratio of total SiGe area to whole wafer was less than 10%, the wafer bending was acceptable small for the following lithographic limitation. Therefore, a well-designed ratio of global SiGe area to whole wafer area is important to avoid large wafer warpage in the integration of the SiGe and MSA. We also came out the critical SiGe area to avoid the defect formation in the underlying Si substrate during the MSA. With the local SiGe area size smaller than 0.2um2, upon MSA there is no defect formation in the underlying Si and the junction leakage could be controlled as low as those of the non-MSA process. Therefore, a well-designed ratio of the global SiGe area to the whole wafer and local SiGe area size were proposed for the 28nm CMOSFETs volume production. Secondly, for the channel engineering of epitaxial strained SiGe, a novel technique to create the suspending stacked gate oxide and subsequently to fill in an embedded SiGe channel (ESC) between the gate oxide and under-layered silicon substrate has been proposed for the first time to fabricate the 28nm PMOSFETs. Without the Si surface passivation on the embedded SiGe channel, such an ESC structure could achieve p-FETs transconductance (Gm) gain of 26% higher as well as Ion_Ioff performance gain of 8% higher than those of conventional strained Si p-FETs with the S/D SiGe. Better S/D resistance (Rsd) in the resistance versus gate length plot and improved swing slop of Id_Vgs plot indicates the higher mobility in the ESC devices. Moreover, the off-state gate current and reliability stressing of the ESC structure are also comparable to the conventional ones. From the X-ray photoelectron spectrum (XPS) analysis, only the Si-O bonding and no Ge-O bonding at the SiGe/SiO2 interface could be accounted for this superior gate oxide integrity for the ESC and strained Si structure. Therefore, such a novel technique with an ESC structure is very promising for the 28 nm pMOSFETs devices and beyond. Finally, the strained SiGe source/drain (S/D) and the novel embedded SiGe channel of the PMOSFETs with the structure and technique improvement are promising to boost device performance for the 28 nm node and beyond.
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