標題: N型無接面多晶矽薄膜電晶體之製作與特性分析
Fabrication and Characterization of N-Type Junctionless Poly-Si Thin-Film Transistors
作者: 鄭靜玲
Cheng, Ching-Ling
Lin, Horng-Chih
Huang, Tiao-Yuan
電子工程學系 電子研究所
關鍵字: 無接面;薄膜電晶體;低壓化學氣相沉積系統;磷偏析;次微米通道長度;邊襯;多頻電容-電壓量測;臨場摻雜;閘極所引起的源極漏電流;多晶矽;固定電荷密度;短通道效應;Junctionless (JL);Thin-film transistor (TFT);Low Pressure Chemical Vapor Deposition (LPCVD);Segregation of phosphorous species;Sub-Lithographic Channel Length;Sidewall spacer;Multi-Frequency C-V Measurements;In situ doping;Gate-Induced Drain Leakage (GIDL);Poly-Si;Fixed charge density;Short-channel effects (SCEs)
公開日期: 2012
摘要: 本篇論文主要針對無接面多晶矽薄膜電晶體的電性與製程微縮兩大主軸來進行探索與討論。在第一個主軸,我們探討了製程參數影響N型無接面多晶矽薄膜電晶體電性之原因,其中,包含了改變通道的摻雜濃度與分別利用水平型和垂直型低壓化學氣相沉積系統(Low Pressure Chemical Vapor Deposition, LPCVD)不同製程下製備元件的通道。實驗結果主要包含了三個部分的探討:首先,針對基本的I-V特性,探討均勻度與短通道的效應。實驗結果顯示,當通道摻雜濃度增加時,除了元件電性具有較差的均勻度與較難被關掉的特性之外,汲極所引致能障降低(Drain-Induced Barrier Lowering, DIBL)現象也較為明顯。另外,當通道摻雜濃度太高時,也會使得載子受到較嚴重的散射,導致開啟狀態的電流(ION)劣化之情形。而在漏電流方面,較大的摻雜濃度也使得電子從價帶穿越能帶間隙到達導帶(Band-to-Band Tunneling)較容易發生,導致較為明顯的閘極所引起的源極漏電流(Gate-Induced Drain Leakage, GIDL)現象。再者,以垂直型LPCVD比水平型LPCVD所製備通道的元件具有較佳的製程均勻度與較佳的短通道效應控制,主要歸因於垂直型LPCVD具有動態可旋轉的沉積腔體與較佳的氣流控制。第二,藉由C-V量測,萃取出相關製程參數,如:通道摻雜濃度,平帶電壓,固定電荷密度,等效氧化層厚度。其中,通道摻雜濃度與固定電荷密度由C-V所萃得分別約為1E19 cm^-3 與 1E12 cm^-2,其中固定電荷密度為負值,推測可能由於在該通道與氧化層界面的磷偏析(segregation)所致。第三部分則是討論元件在高溫下操作的效應,實驗結果顯示以水平型LPCVD製備通道的元件有較好的穩定性,推究造成此一結果可能歸因於在垂直型LPCVD沉積的元件通道有較嚴重的磷偏析所致,除此之外,我們也進一步萃取了活化能並加以討論。 另一個主軸則是以新穎的結構利用邊襯(Sidewall Spacer)的方式以I-line光學步進曝光機成功製作出通道長度(L)可小於0.1微米的N型無接面多晶矽薄膜電晶體。在均勻度方面,可以發現當光罩上所定義的通道長度(L_mask)愈短,其元件具有較差均勻性,顯示邊襯的變異對於短通道元件的影響甚大。此外,開啟狀態的電流與通道長度的相關性在短通道元件中則更為明顯,推測其原因可能為受到源/汲極串聯電阻的影響所致。特別的是,在此研究中,除了一般的電性結果外,我們還加入了簡單的統計所做出的定性結果來進一步分析與討論在製程微縮下的元件之電性表現。再者,我們同樣利用C-V方式萃取以此方式製作的元件的通道摻雜濃度與固定電荷密度,所萃取出的通道摻雜的濃度與固定電荷密度由C-V所萃得同樣約為1E19 cm^-3與1E12 cm^-2,其中固定電荷密度也為負值,與上述舊有的結構結果相似。
In this thesis, we have fabricated in situ n-type junctionless (JL) poly-Si thin-film transistors (TFTs) and aimed at investigating the electrical properties of the devices and developing a fabrication process capable of fabricating devices with sub-lithographic channel length. First, we used either vertical or horizontal low pressure chemical vapor deposition (LPCVD) to prepare the channel films with various deposition conditions. The fundamental I-V device characteristics, including variation in device characteristics and short-channel effects (SCEs), were studied. Experimental results show that devices show worse uniformity and drain induced barrier lowering (DIBL), and are more difficult to turn off as the channel doping concentration increases. The increasing channel doping concentration would further degrade SS at high VD, owing to the weaker shielding of the channel region from the electric field originating from the drain. In addition, it is obviously seen that on current degrades for the device with higher channel doping concentration. This implies that carriers in the channel suffer from severer scattering when channel doping is increased. Also, it can be seen that GIDL leakage increases when the channel doping concentration increases. Such results can be attributed to the fact that band-to-band tunneling increases and leads to a high off current. Furthermore, the process uniformity is much better for the devices with channel prepared by vertical LPCVD. These differences can be attributed to the design of reactors. It's well known that the vertical LPCVD is usually more sophisticated, and has better control on gas flow dynamics and the capability for wafer rotation during the deposition. Second, in C-V measurements, major electrical parameters such as channel dopant concentration, flat-bland voltage, gate oxide thickness, and fixed charge density can be extracted from C-V analysis. The carrier concentration and negative fixed charge density at the channel/oxide interface are approximately about 1E19 cm^-3 and 1E12 cm^-2, respectively. The negative fixed oxide is presumably due to the segregation of phosphorous at the channel/oxide interface. Finally, we also investigate the high temperature characteristics of our fabricated JL devices. Experimental results show that devices with channel prepared by the horizontal LPCVD show much better stability than that prepared by the vertical LPCVD. It is attributed to the more severe segregation of phosphorous species in the case of vertical LPCVD. Also, the activation energy is extracted and discussed. On the other hand, we aimed at developing a new process for fabricating short-channel devices. The new structure employs “spacer” etching to shorten the channel length (L) down to 0.1μm by using an I-line stepper. Experiments show that the sidewall spacer draw critical impact on the channel length defined by “mask” (Lmask).Also, on current dependence on L becomes more and more important as L decreases. The reason behind is related to the RSD which becomes more important as the device is scaled down. Apart from the electrical results, a simple qualitative analysis of devices is presented and discussed. In addition, from C-V measurements, the carrier concentration and negative fixed charge density at the channel/oxide interface are approximately about 1E19 cm^-3 and 1E12 cm^-2, respectively. The results are consistent with those obtained from the devices of old structure and reasonable because the channel preparations of these devices are actually the same.