標題: 透明非晶態氧化銦鋅錫薄膜電晶體技術之研究
Study on Novel Transparent Amorphous Indium Zinc Tin Oxide Thin Film Transistors Technology
作者: 黃韋勳
Huang, Wei-Hsun
劉柏村
Liu, Po-Tsun
光電工程研究所
關鍵字: 非晶態氧化物半導體;氧化銦鋅錫;薄膜電晶體;半導體元件可靠度;閘極偏壓應力;雙主動層結構;amorphous oxide semiconductors;indium-zinc-tin-oxide (IZTO);thin-film transistors (TFTs);semiconductor device reliability;gate bias stress;dual active layer structure
公開日期: 2012
摘要: 近年來,非晶態氧化銦鎵鋅薄膜電晶體 (a-InGaZnO TFTs) 在相關的研究領域上得到相當大的矚目。這是因為相較於傳統的氫化非晶矽 (a-Si:H) 半導體,它們擁有更高的載子遷移率以及更理想的可靠度。除此之外,在材料均勻性與製程光罩成本上,它們也有著許多優於多晶矽半導體的地方。因此,非晶態氧化銦鎵鋅薄膜電晶體擁有可以滿足下一代新型顯示器發展需求的潛力。然而,鎵離子的存在與元素特性的限制使得這種類型的材料難以繼續在載子遷移率上得到進一步的提升。為了因應立體電視及可撓式電子產品等新型顯示器對於高畫素切換速率的迫切需求,在本研究中,我們開發出高載子遷移率的非晶態氧化銦鋅錫薄膜電晶體 (a-InZnSnO TFTs)。 在一開始,我們對非晶態氧化銦鋅錫薄膜電晶體在不同退火條件下的材料特性及電特性表現進行分析。在這期間我們發現到,適當的退火溫度及時間可以修復主動層中的缺陷並改善品質,進而提升元件的電特性。除此之外,退火時不同氣氛的引入也會影響元件特性。當退火氣氛為氧氣或氮氣時,可以填補背通道中的氧空缺,降低退火期間鋅離子的散失,以及抑制元件過導通的現象。 接著,我們藉由stretched-exponential模型 (the stretched-exponential model),來驗證正閘極偏壓應力 (Positive Gate Bias Stress : PGBS) 是如何影響元件臨界電壓的變異並降低元件的可靠度。這套物理機制與載子注入並隨即被缺陷捕獲的概念相關。經由相關驗證我們發現到,適當的退火溫度改善了元件的可靠度。 另一方面,為了進一步提升元件對環境的穩定度,我們結合導通性較佳的氧化銦鋅錫薄膜以及 穩定性較佳的氧化銦鎵鋅薄膜,並提出雙主動層的元件結構。具有雙主動層結構的元件即使經過相當高溫的退火,仍可讓背通道中的氧空缺得到控制,並進一步改善元件對環境的穩定度以及載子遷移率。最後,雙主動層元件中寄生電晶體效應的降低與沉積元件背通道時的高氧氣流量以及較薄的背通道厚度有關,這些過程可以讓元件背通道的絕緣性提高並進一步改善元件對環境的穩定性。
During the recent years, there have been great interests in studying amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs). Because a-IGZO TFTs have higher carrier mobility and better reliability than traditional covalent bond semiconductors (e.g., a-Si:H). Furthermore, its uniformity and the cost of masks are more attractive than poly-Si based TFTs. Therefore, a-IGZO TFTs have possessed the potential for next generation novel flat panel display development. However, a-IGZO TFTs including Ga3+ content are hard to further promote higher carrier mobility because of the material properties. In order to achieve enough high frame rates for novel application such as 3D TV and flexible electronic products, we substituted gallium via tin and exploited high-mobility amorphous In-Zn-Sn-O thin film transistors (a-IZTO TFTs) In the beginning, we have surveyed the thin film characteristics and electrical performance of a-IZTO TFTs with different annealing temperature, atmosphere, and time. Moderate annealing time and temperature resulted in the improved quality of a-IZTO thin film and the enhanced electrical performance from the repaired defect states. Additionally, the post-annealing environment also influenced a-IZTO TFTs. Annealing with O2 or N2 gas in atmosphere could eliminate the oxygen vacancy in the back channel, reduce the loss of Zn2+ during annealing, and suppress the excessive conduction phenomenon. Then, we modeled how PGBS caused threshold voltage variation by demonstrating the stretched-exponential model that traced back to the carrier injection / trapping concept. This physical mechanism might cause the unstable reliability during gate bias stress. Consequently, suitable temperature annealing improved the reliability of the devices. On the other hand, for promoting the ambient stability of a-IZTO TFTs, we combine a conductive a-IZTO layer and a stable a-IGZO layer and proposed the dual active layer structure. The devices with dual active layer structure could successfully suppress excessive conduction, improve the ambient stability, and promote carrier mobility of devices for 400oC N2 annealing process. Finally, the decrease of parasitic transistors effect in dual active layer devices was achieved by higher O2 flow during deposition and thinner back active layer, which made it more insulated and better ambient stability.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070050529
http://hdl.handle.net/11536/71922
Appears in Collections:Thesis