標題: 利用雜訊抵消技術之Ku-Band低雜訊放大器設計與分析
Design and Analysis of Ku-Band Low Noise Amplifier Exploiting Noise Cancellation
作者: 鄧駿逸
Teng, Chun-Yi
周復芳
Jou, Christina F.
電機學院電信學程
關鍵字: 低雜訊放大器;雜訊抵消;Low Noise Amplifier;Noise Cancellation
公開日期: 2012
摘要: 本論文以TSMC 0.18µm 1P6M CMSO,來研製應用於Ku Band(12~18GHz)寬頻低雜訊放大器。第一部份為低電壓低耗電Current Reused架構之寬頻低雜訊放大器。量測結果如下所述:工作電壓為1V,S11與S22都小於-9dB,Gain為9.75dB,NF(min)為5.0dB,,在15GHz的P1dB為-12dBm,IIP3為-3dBm,核心電路耗電為4.35mW(不包括緩衝器耗電),晶片總面積為0.63 mm2;第二部份是增加CS來達到Noise Cancelling的效果,量測結果如下:工作電壓為1.2V,S11與S22都小於-9dB,Gain為9dB,NF(min)為3.66dB,,在15GHz的P1dB點為-15dBm,IIP3為 -6dBm,核心電路耗電為8.12mW(不包括緩衝器耗電),晶片總面積為0.55 mm2;第三部份是使用Transformer來達到Noise Cancelling的效果,Post-Simulation結果如下:工作電壓為1.2V,S11與S22都小於-8.5dB,Gain為13.81dB,NF(min)為3.36dB,,在15GHz的P1dB點為-17dBm,IIP3為-8dBm,核心電路耗電為6.72mW(不包括緩衝器耗電),晶片總面積為0.33 mm2。
In this thesis, we design 12~18GHz Ku Band low noise amplifier using by using TSMC 0.18um CMOS 1P6M process. In the first part, the chip is wideband low noise amplifier under the frame of low-voltage an low-power consumption current reused.The results of measurements are as follows : operation voltage is 1V, input matching S11 and output matching S22 are both less then -9dB, gain is 9.75dB, noise figure(min) is 5.0dB, P1dB is -12dBm under 15GHz, IIP3 is -3dBm, core power consumption is 4.35mW(not including output buffer), and the chip size is 0.63 mm2 . In the second part, we implemnet CS stage to achieve noise cancelling effect. The measurements are as follows : operation voltage is 1.2V, input matching S11 and output matching S22 are both less than -9dB, gain is 9.0dB, noise figure(min) is 3.66dB, P1dB is -15dBm under 15GHz, IIP3 is -6dBm, core power consumption is 8.12mW(not including output buffer), and the chip size is 0.55 mm2 . In the third part, we use transformer to achieve noise cancelling effect. Theresults of post-Simulation are as follows:operation voltage is 1.2V, input matching S11 and output matching S22 are both less than-8.5dB, gain is 13.81dB, noise figure(min) is 3.36dB, P1dB is -17dBm under 15GHz, IIP3 is -8dBm, core power consumption is 6.72mW(not including output buffer), and the chip size is 0.33 mm2
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079667544
http://hdl.handle.net/11536/71912
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