|標題:||CMOS 5-500MHz 低相位抖動鎖相迴路之頻率合成器|
A PLL of Low Jitter 5-500MHz for Frequency Synthesizer in CMOS Process
本論文所提出的鎖相迴路是TSMC 0.6μm 製程技術,設計一個寬廣的操作頻率和低相位抖動特性的頻率合成器。在寬廣的操作頻率功能上,利用可改變電流的電荷幫浦去補償因除頻器或參考頻率改變時所影響的阻尼參數，讓阻尼參數保持在固定的值。在低相位抖動功能上,本論文提出造成相位抖動的幾個因素，包括相位頻率偵測器和電荷幫浦的不理想狀態，如何改善這些影響相位抖動的問題在此論文亦有詳述。利用一新架構之相位頻率偵測器改善電流開關太頻繁造成耗電和相位抖動的問題；利用正回授的差動式電荷幫浦使因雜散電容造成之相位抖動問題減小並且降低頻率鎖定的時間。
整個電路模擬結果顯示工作頻率範圍從5MHz 到500MHz ﹔相位抖動峰對峰值為76.55ps，平均值為13.25ps，功率損耗小於30mW。在頻率50MHz 到500MHz之間的相位鎖定時間小於10μs；在5MHz 的相位鎖定時間須要30μs。|
Phase locked loop (PLL) are used in so many different application. Examples of applications that use PLL include clock and data recovery, clock synthesis or synchronization, frequency synthesis, and PLL modulator or de-modulator applications. This thesis describes the design of a Phase Locked Loop is used to be a frequency synthesizer between internal and external clock for the function of locking the internal and external clock phase to reduce the time delay between them. The PLL is fully integrated onto TSMC 0.6um CMOS process that is designed by synthesis function of low jitter performance and wide frequency operating. For wide operation frequency, the damping factor in phase loop is a very important We choose charge pump current to be compensating parameter that caused by the large variation of N value programmable divider or large variation of reference frequency. The effect of variable charge pump current comes out to be evident since the variation of becomes acceptable and phase margin of loop is also satisfactory. For low phase jitter performance, the charge pump, however, shows non-ideal behavior when implemented in the circuit and its practical issues need to be considered. The non-ideal effects of the charge pump /PFD includes the leakage current, the mismatch, the delay offset in the PFD and the parasitic capacitances. In the thesis research, we adopted a true single-phase detector for getting a low jitter performance that UP and DN signals pulse width is reduced to approximated half size of the conventional NAND type PFD. And a positive feedback CMOS charge pump is adopted to improve the charge-sharing problem and increase switching speed. The simulation results show the PLL with an operating range of 5MHz to 500MHz, peak to peak jitter of 76.55ps with 13.25ps RMS at 500MHz and power dissipation less than 30 mW. The phase locking time is less than 10us in the frequency of 50MHz to 500MHz, and 30us in 5MHz.
|Appears in Collections:||Thesis|