Title: 應用類比電路設計及覆晶封裝技術於毫米波高速電子遷移率電晶體之收發機
Millimeter-Wave HEMT Transceiver With Analog Circuit Design Approach and Flip-Chip Technology
Authors: 蘇珍儀
Su, Jen-Yi
孟慶宗
Meng, Chin-Chun
電信工程研究所
Keywords: 高速電子遷移率電晶體;多重相位濾波器;混頻器;共平面波導管;覆晶封裝;接收機;降頻器;除頻器;high electron mobility transistor;polyphase filter;mixer;coplanar waveguide;flip-chip;receiver;down-converter;divider
Issue Date: 2008
Abstract: 在本論文中,是以0.15微毫米砷化鎵(GaAs)假晶格高速電子遷移電晶體(pHEMT)及變形晶格高速電子遷移電晶體(mHEMT)來設計毫米波頻段的類比積體電路與單晶微波積體電路。這些砷化鎵的技術具有高崩潰電壓,截止頻率,低雜訊,高輸出功率和半絕緣基板的優點。除此,高頻電路的封裝技術也很重要,在此採用覆晶封裝技術來驗證V頻段的放大器在封裝前後有一樣的特性。 在第二章中,使用0.15微毫米砷化鎵pHEMT來提出設計在Ku跟Ka頻帶的三種吉伯特混頻器。由於半絕緣的砷化鎵基版,微波被動元件具低損耗而且多重相位濾波器可以操作在較高的頻段。利用高精確的氮化鉭薄膜式電阻可設計多重相位濾波器而產生完美的正交相位。因此,我們所提出的15 GHz單頻帶升頻器具有63 dB的單邊頻帶消除比率,另一個34 GHz 次諧波正交輸出的降頻器可達到小於0.4 dB的振幅與1˚相位的誤差,且超過50 dB的本端振盪源(LO)洩漏壓制。再者,提出40 GHz次諧波堆疊式-LO電路使用補償式技術來解決延遲時間的問題而且比較我們之前所發表論文可以減少電晶體數量。 在第三章比較Q頻帶0.15 微毫米 PHEMT及mHEMT 的次諧波堆疊式-LO升頻器在增益,隔絕度及線性度上的差異。一般來說,0.15微毫米mHEMT 的元件比pHEMT具有較高的轉導和截止頻率。所以在設計主動吉伯特混頻器,使用mHEMT製程的轉換增益應該會比pHEMT來的大。利用pHEMT及mHEMT製程來設計Q頻帶的次諧波堆疊式-LO升頻器,經量測分別有-7.1 dB及-0.2 dB的轉換增益。pHEMT的升頻器有-12 dBm的輸出三階截止點和-24 dBm的輸出1dB壓縮點,此時mHEMT 線性度改善有4 dB在於輸出1dB壓縮點與輸出三階截止點的差值。 在第四章節展現V頻帶的共平面波導-微帶線-共平面波導兩級放大器結合覆晶封裝技術。為了配合覆晶封裝的結構,輸入與輸出端則設計共平面波導,而中間級則採用微帶傳輸線來減少晶片面積。在這兩級放大器著重是在第一級利用電晶體當作共平面波導轉換成微帶線,及在第二級利用電晶體將微帶線轉換成共平面波導。共平面波導-微帶線-共平面波導轉換的兩級放大器在53 GHz有14.8 dB的增益,10 dB及22 dB的輸入及輸出反射係數。經過覆晶封裝後的量測放大器特性也跟沒有覆晶封裝前幾乎差不多。 在第5章節說明使用mHEMT製程設計一個60 GHz單晶微波積體電路接收機。接收機包括一個LO 倍頻串,60 GHz 鏡像消除二極體混頻器及一個60GHz的三級低雜訊放大器。LO倍頻串的形成是採用一個乘三器及一個三級的回授放大器。而60GHz的鏡像消除混頻器則採用對稱式的次諧波二極體混頻器且結合了IF及三倍LO頻率的正交分合波器。這60 GHz mHEMT接收機有5 dB的轉換增益,7 dB的雜訊指數和22 dB的鏡像消除比率。且有-24 dBm的輸入1dB壓縮點和-16 dBm的輸入三階截止點。 第六章節報告用pHEMT製程設計在Ka頻帶正交輸出除二的米勒除頻器。架構是基於一個正向回授的迴路,包含了一個馬爾尚巴倫,兩個乘法器和LC槽濾波器。除頻器使用單邊頻帶升頻器來驗證正交輸出的精確度。可達到35 dB的旁波帶消除比率。最小的輸入靈敏度是2.7 dBm,可除的頻寬從32到36 GHz比率是12%。
In this dissertation, all analog integrated circuits and monolithic microwave integrated circuits (MMICs) are demonstrated using 0.15-□m pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) technologies. These GaAs-based technologies have the advantages of a high breakdown voltage, cutoff frequency, low noise figure, higher output power, and semi-insulating substrate. Furthermore, a package technique is an important key for high-frequency circuits. The flip-chip technique is demonstrated that the performances of V-band amplifiers with and without flip-chip are almost the same. In Chapter 2, three kinds of Ka/Ku-band Gilbert mixers are demonstrated using pHEMT technology. Thanks to the semi-insulating GaAs substrate, microwave passive components have a low-loss feature, and polyphase filters work up to higher frequencies. Highly accurate Tantalum Nitride (TaN) thin film resistors utilized in polyphase filters result in perfect quadrature operation. Therefore, our proposed single-sideband up-converter operates at 15 GHz with a 63-dB sideband rejection ratio, and another 34-GHz I/Q subharmonic down-converter reaches < 0.4-dB magnitude and < 1° phase errors. More than 50-dB LO leakage suppression is achieved in the I/Q subharmonic mixer. On the other hand, a 40-GHz stacked-LO subharmonic mixer with a novel compensation technique is also proposed and demonstrated to improve LO speed and reduce the amount of transistors as compared to the previous work. Chapter 3 makes a comparison between Q-band 0.15 μm pHEMT and mHEMT stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 μm mHEMT device has a higher transconductance and cutoff frequency than a 0.15 μm pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of -7.1 dB and -0.2 dB, respectively. The pHEMT upconversion mixer has an OIP3 of -12 dBm and an OP1dB of -24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the OIP3 and OP1dB. In Chapter 4, the V-band coplanar waveguide (CPW)-microstrip line (MS)-CPW two-stage amplifier with the flip-chip bonding technique is demonstrated. The CPW is used at input and output ports for flip-chip assemblies and the MS transmission line is employed in the interstage to reduce chip size. This two-stage amplifier employs transistors as the CPW-MS transition and the MS-CPW transition in the first stage and the second stage, respectively. The CPW-MS-CPW two-stage amplifier has a gain of 14.8 dB, input return loss of 10 dB and output return loss of 22 dB at 53.5 GHz. After the flip-chip bonding, the measured performances have almost the same value. A 60 GHz single-chip receiver MMIC using 0.15-μm mHEMT technology is demonstrated in Chapter 5. The receiver consists of an LO multiplier chain, a 60 GHz three-stage low noise amplifier, and 60 GHz image rejection diode mixer. The LO chain is formed with a tripler and a 28 GHz three-stage feedback amplifier. Furthermore, the 60 GHz image rejection mixer is a symmetrical subharmonic diode mixer and integrated with IF and 3 × LO quadrature hybrids. The mHEMT receiver has the conversion gain of 4 dB, the noise figure of 7.0 dB, and the image rejection ratio of 22 dB at 60 GHz. The -24 dBm IP1dB and -16 dBm IIP3 are measured. Chapter 6 reports a Ka-band quadrature-output divide-by-two Miller divider using the 0.15-μm pHEMT technology. The circuit topology consists of one Marchand balun, two active multipliers and LC-tank filters with a positive feedback loop. The divider includes a single side-band (SSB) up-converter to verify the quadrature accuracy of the divider’s outputs. A 35-dB side-band rejection ratio is achieved. The minimum input sensitivity equals 2.7 dBm. The stable division from 32 to 36 GHz in a bandwidth of 12 % can be obtained.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009213817
http://hdl.handle.net/11536/70945
Appears in Collections:Thesis


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